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Host interface:

  • Parallel DPM = DPM: 8/16-bit, multiplexed/non-multiplexed
  • Serial DPM = SPM: SPI/SQI, SPO/SPH=0/1, SPO/SPH=1/1

When a write access during the last bit of a data byte is aborted (CS deasserted), it will still perform a write into INTRAM.

The written data is incorrect. The content of the last data bit = state of the MOSI signal (SPM) or data signals (DPM) during access abort.


  • When a write access was started and not properly completed as supposed, it is impossible to surely prevent that no data is written in the netX (for both SPM and DPM access).

No workaround, despite completing the write access properly as supposed

 Example: SPM access in SPI slave mode