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Q

Why does the hardware watchdog not reset the device?

A

In the "Technical data reference guide" revision 5 in chapter "3.12 Watchdog" the hardware watchdog unit is explained.

In "Table 9" the escalation paths of the watchdogs are shown.

Together with "Figuer 12" you are able to see, that the watchdogs available on application side escalate to the communication side.

Only the communication side is able to reset the chip. So the communication sides watchdog has to be configured and used. The FAQ on Software Reset has to be considered.

Q

What is the intended way to reset the device?

A

The FAQ on Software Reset describes this.

Q

Why is the hardware watchdog on communication side not used?

A

For debugging and diagnostic purposes it is not feasible to reset the chip if an error occurs. The protocol stacks contain their own watchdog mechanisms to deal with non responsive systems. You might like to take a look into DPM - Dual Port Memory - Channel Watchdog.

Another reason is explained in the FAQ for the Software Reset.

Q

Do you have some example code on the watchdog even if it does not reset the chip?

A

Of course, here it is. But if you consider to reset the chip on your own please have a look into Software Reset.

Watchdog example
#include "Examples.h"
#include "netx_drv.h"

static uint32_t ulEscalate = 0;
static uint32_t ulOld;

void WDG_IRQHandler()
{
  uint32_t ulNew = systime_app->systime_ns;
  if(!ulEscalate)
  {
    wdg_app->netx_sys_wdg_ctrl_b.wdg_counter_trigger_w = 1;
  }
  TRACE(DRV_TRACE_KEY_COUNTER, wdg_app->netx_sys_wdg);
  TRACE(DRV_TRACE_KEY_LENGTH, (ulNew - ulOld) / 1000000);
  ulOld = systime_app->systime_ns;
  if(wdg_app->netx_sys_wdg==0x7d0){
    wdg_app->netx_sys_wdg_ctrl_b.write_enable = 1;
    wdg_app->netx_sys_wdg_irq_timeout = 0;
    wdg_app->netx_sys_wdg_res_timeout = 0;
    wdg_app->netx_sys_wdg_ctrl_b.irq_req_watchdog = 0;
  }
}

int wdgexample(int argc, const char* argv[])
{
  DRV_NVIC_EnableIRQ(wdg_app_IRQn);
  DRV_NVIC_SetPendingIRQ(wdg_app_IRQn);
  wdg_app->netx_sys_wdg_irq_msk_reset_b.wdg_res_irq = 1;
  wdg_app->netx_sys_wdg_ctrl_b.write_enable = 1;
  wdg_app->netx_sys_wdg_irq_timeout = 1000;
  wdg_app->netx_sys_wdg_res_timeout = 1000;
  wdg_app->netx_sys_wdg_ctrl_b.write_enable = 0;
  wdg_app->netx_sys_wdg_ctrl_b.wdg_counter_trigger_w = 1;
  wdg_app->netx_sys_wdg_ctrl_b.irq_req_watchdog = 1;
  return 0;
}

int wdgescalate(int argc, const char* argv[])
{
  ulEscalate=1;
  return 0;
}

int wdgdeescalate(int argc, const char* argv[])
{
  ulEscalate=0;
  wdg_app->netx_sys_wdg_ctrl_b.wdg_counter_trigger_w = 1;
  return 0;
}