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The netX 90 is a multiprotocol communication SoC with built-in motor control for motion and drive applications, featuring up to 1.5 MB Flash memory, integrated Ethernet PHYs, built-in security and diagnostics, on-chip DC/DC converter with POR circuit, analog BOD function for higher voltages, and a feature-rich set of on-chip peripherals with connectivity. As illustrated in Figure 1, the SoC architecture is composed of a communication subsystem (left-hand side), a block of shared functions (bottom, center), and an application host (right-hand side):

  • The communication segment features two flexible communication (xC) channels with switch and IEEE 1588 support for all widely used industrial real-time communication protocols.
  • The block of shared functions serves both segments of the chip, depending on the application use case. Integrated firewalls in front of each shared peripheral regulate access rights.
  • The appplication segment features a second Cortex®-M4 at 100 MHz with DSP and FPU support, enhanced by a set of on-chip peripherals for motion and motor control applications.


Figure 1: netX 90 block diagram with highlighted motion and motor control related peripheral features

The data exchange with the protocol stack interface using the internal DPM (iDPM) eliminates access latencies for single-cycle CPU access. The virtual DPM comprises up to 32 KB SRAM with handshake cell registers and IRQ support, including a hardware-assisted network synchronization generated by the xC trigger unit. The exact use of the hardware-assisted synchronization depends on the supported feature-set of the real-time communication protocol standard and the underlying device configuration for the network connection with the PLC.

Figure 2: Hardware-assisted synchronization between FOC, MPWM, MADC, and PSE for application profiles

The built-in motion and motor control application enables for instance the implementation of a field-oriented control (FOC) algorithm with position feedback to drive a 3-phase PMSM or BLDC motor. The supported peripheral feature-set includes:

1. Motion Pulse-Width Modulation (MPWM):

  • 6+1 channel MPWM
    • 10 ns resolution
    • “Classic” center aligned mode
      • Automatic dead-time insertion, 0% and 100% duty cycle support
    • Software defined free form mode
      • Arbitrary dead time compensation algorithms
    • Update every half, full or nth period
      • Low to high PWM frequency with single IRQ per current control loop
    • FAULT input independent of clock

2. Motion Analog-to-Digital Converter (MADC):

  • 4x ADC with sample & hold
    • 12-bit resolution and up to 2 MS/s
    • 20 input channels (2+2+8+8)
    • Simultaneous measurement of
      • 2 of 3 motor currents and one SinCos encoder
      • 2 SinCos encoders
  • 4x ADC controller with DMA
    • 8 triggers per ADC
    • Triggers on PWM phase, 6 dead times or network
  • Up to 32 (8x4) measurements per PWM (half) cycle with a single IRQ per current loop, e.g. motor currents, phase voltages, DC-Link, 2x SinCos, temperature, etc.

3. Motion Encoder (MENC) Interface:

  • 2x quadrature encoder interfaces
    • 3 input channels (A, B and N) per encoder module
    • 2 encoder filters
    • 4 capture units
  • High resolution for more accurate determination of position or speed
  • Zero reference input for the precise determination of an absolute reference position
  • A digital glitch filter to reduce the impact of system-generated noise

4. EnDat 2.2 Interface for Encoders:

  • 2x EnDat master E6 basic interfaces
    • Supported protocols EnDat2.2 and SSI
    • Clock rate of up to 16 MHz

5. BiSS Interface for Encoders:

  • 2x BiSS MB-100 master interfaces

    • Supported protocols BiSS C and SSI
    • Cyclic transfer at data rates of up to 10 Mbit/s

6. Enhanced GPIOs with Timer:

  • 8x GPIO with event counters
    • Event time capture
    • Active time measurement
  • Capture counter on edge or level
    • Capture counter once or continuously
    • Count external events (edges or duration of level)
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