Register Definition


Base Address Areas

Name Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
intflash2_mirror_app_boot 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
intram6 0x000b0000 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 . . . . . . . . . . . . . . .
intram7 0x000b8000 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 . . . . . . . . . . . . . . .
intflash2 0x00200000 0 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . . . . . . . . . . . . .
sdram 0x10000000 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
intram6_mirror_sram 0x200b0000 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 . . . . . . . . . . . . . . .
intram7_mirror_sram 0x200b8000 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 . . . . . . . . . . . . . . .
intram6_mirror_ocp 0x400b0000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 . . . . . . . . . . . . . . .
intram7_mirror_ocp 0x400b8000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 . . . . . . . . . . . . . . .
sqirom 0x64000000 0 1 1 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
extsram 0x68000000 0 1 1 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
idpm_slave 0x70000000 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . .
sqirom_mirror_ext_peri 0xa4000000 1 0 1 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
extsram_mirror_ext_peri 0xa8000000 1 0 1 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
idpm_slave_mirror_ext_peri 0xb0000000 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . .
cm4_private_peripherals 0xe0000000 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . .
cm4_itm 0xe0000000 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
cm4_dwt 0xe0001000 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . .
cm4_fpb 0xe0002000 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . . . . . .
cm4_scs 0xe000e000 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 . . . . . . . . . . . .
cm4_etm 0xe0041000 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 . . . . . . . . . . . .
cm4_cti 0xe0042000 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . . . . . . . . . .
cm4_misc_ctrl 0xe0043000 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 . . . . . . . . . . . .
idpm_com 0xff001b00 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 . . . . . . . .
crypt 0xff080000 1 1 1 1 1 1 1 1 0 0 0 0 1 . . . . . . . . . . . . . . . . . . .
hash 0xff080000 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . .
aes 0xff080080 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . .
random 0xff0800c0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 . . .
mtgy 0xff082000 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 . . . . . . . . . . . . .
intlogic_shd 0xff400000 1 1 1 1 1 1 1 1 0 1 0 0 0 . . . . . . . . . . . . . . . . . . .
nfifo 0xff400000 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
pad_ctrl 0xff401000 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . . . . . .
asic_ctrl 0xff401200 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 . . . . . . . .
mmio_ctrl 0xff401300 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 . . . . . . .
global_buf_man 0xff401380 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 . . . . . .
iflash_cfg2 0xff401400 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 . . . . . . .
hif_io_ctrl 0xff401480 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 . . . . . .
hifmemctrl 0xff401500 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 . . . . . . . .
hif_asyncmem_ctrl 0xff401500 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 . . . . . .
hif_sdram_ctrl 0xff401540 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 . . . . . .
hifmem_priority_ctrl 0xff401580 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 . . . . . .
abort 0xff401600 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 . . . .
sqi 0xff401640 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 . . . . . .
sample_at_porn_stat 0xff401680 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 . . . .
adc_seq 0xff4016c0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 . . . . . .
miimu 0xff401700 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 . . . .
feth 0xff480000 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 . . . . . . . . . . . . . . . .
eth_system 0xff480000 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 . . . . . . . . . . . . . . . .
eth 0xff480000 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . .
intlogic_app 0xff800000 1 1 1 1 1 1 1 1 1 0 0 0 0 . . . . . . . . . . . . . . . . . . .
dmac_app 0xff800000 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
dmac_app_ch0 0xff800100 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . .
dmac_app_ch1 0xff800120 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 . . . . .
dmac_app_ch2 0xff800140 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 . . . . .
dmac_app_reg 0xff800800 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . .
dmac_mux_app 0xff801000 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . .
uart_app 0xff801040 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 . . . . . .
i2c_app 0xff801080 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . . . .
mled_ctrl_app 0xff801100 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . . . .
ecc_ctrl_app 0xff801200 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 . . . . . . . . .
gpio_app 0xff801400 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 . . . . . . . .
systime_lt_app 0xff801540 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 . . . . . .
timer_app 0xff801580 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 . . . . . . .
systime_app 0xff801600 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 . . . .
mcp_app 0xff801620 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 . . . . .
wdg_app 0xff801640 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 . . . . .
trigger_irq_app 0xff801660 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 . . . . .
endat0_app 0xff801700 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 . . . . . .
endat1_app 0xff801740 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 . . . . . .
endat_ctrl0_app 0xff801780 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 . . . .
endat_ctrl1_app 0xff801790 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 . . . .
can_ctrl0_app 0xff801900 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 . . . . . . .
can_ctrl1_app 0xff801980 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 . . . . . . .
spi0_app 0xff801a00 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 . . . . . .
spi1_app 0xff801a40 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 . . . . . .
spi2_app 0xff801a80 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 . . . . . .
pio_app 0xff801ac0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 . . . .
biss0_app 0xff801b00 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 . . . . . . . .
biss1_app 0xff801c00 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 . . . . . . . .
biss_ctrl0_app 0xff801d00 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 . . . . .
biss_ctrl1_app 0xff801d20 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 . . . . .
xpic_app_config 0xff880000 1 1 1 1 1 1 1 1 1 0 0 0 1 . . . . . . . . . . . . . . . . . . .
xpic_app_dram 0xff880000 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . . .
xpic_app_pram 0xff882000 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 . . . . . . . . . . . . .
xpic_app_regs 0xff884000 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 . . . . . . .
xpic_app_debug 0xff884080 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 . . . . . . .
xpic_app_system 0xff900000 1 1 1 1 1 1 1 1 1 0 0 1 0 . . . . . . . . . . . . . . . . . . .
vic_xpic_app 0xff900000 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . .
timer_xpic_app 0xff900100 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . .
wdg_xpic_app 0xff900180 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . .
mcp_xpic_app 0xff9001a0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 . . . . .
systime_lt_xpic_app 0xff9001c0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 . . . . . .
gpio_xpic_app 0xff900200 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . .
uart_xpic_app 0xff900300 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . . .
i2c_xpic_app 0xff900340 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 . . . . . .
spi_xpic_app 0xff900380 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 . . . . . .
io_link_xpic_app 0xff900400 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . .
xlink0 0xff900400 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 . . . .
xlink1 0xff900410 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 . . . .
xlink2 0xff900420 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . .
xlink3 0xff900430 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 . . . .
xlink4 0xff900440 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 . . . .
xlink5 0xff900450 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 . . . .
xlink6 0xff900460 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 . . . .
xlink7 0xff900470 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 . . . .
io_link_irq 0xff900480 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 . . . . .
debug_slave 0xffff8000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . .
cssys_rom_table 0xffff8000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 . . . . . . . . . . . .
cssys_tsgen 0xffff9000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 . . . . . . . . . . . .
cssys_cti 0xffffa000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 . . . . . . . . . . . .
cssys_atbfunnel 0xffffb000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 . . . . . . . . . . . .
cssys_tpiu 0xffffc000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 . . . . . . . . . . . .

Base Address Area: intram6, intram6_mirror_sram, intram6_mirror_ocp

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W intram6_base
1-1ffe 4-7ff8 -  reserved
1fff 7ffc R/W intram6_end

intram6_base
(NETX_MEM_INTRN_SRAM6_BASE)
internal SRAM AHBL slave 6 start address
Area size: 32kB
Read accesses in this memory area: 0WS, byte accessable
Write accesses in this memory area: 0WS, byte accessable

Note: For byte- or 16-bit-write-access a read-modify-write is performed
   to update the 32bit ECC. This is normally done in background without
   performance penalty. However sometimes a wait-state could occur for this.
   The 64kB XC memories (INTRAM3 and 4) never produce wait-states. They
   have a 8-bit ECC which avoids read-modify-write.
R/W
0x00000000
Address@intram6 : 0x000b0000
Address@intram6_mirror_sram : 0x200b0000
Address@intram6_mirror_ocp : 0x400b0000
Bits Reset value Name Description
31 - 0 0
intram6_base


intram6_end
(NETX_MEM_INTRN_SRAM6_END)
internal SRAM AHBL slave 6 end address
R/W
0x00000000
Address@intram6 : 0x000b7ffc
Address@intram6_mirror_sram : 0x200b7ffc
Address@intram6_mirror_ocp : 0x400b7ffc
Bits Reset value Name Description
31 - 0 0
intram6_end



Base Address Area: intram7, intram7_mirror_sram, intram7_mirror_ocp

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W intram7_base
1-1ffe 4-7ff8 -  reserved
1fff 7ffc R/W intram7_end

intram7_base
(NETX_MEM_INTRN_SRAM7_BASE)
internal SRAM AHBL slave 7 start address
Area size: 32kB
Read accesses in this memory area: 0WS, byte accessable
Write accesses in this memory area: 0WS, byte accessable

Note: For byte- or 16-bit-write-access a read-modify-write is performed
   to update the 32bit ECC. This is normally done in background without
   performance penalty. However sometimes a wait-state could occur for this.
   The 64kB XC memories (INTRAM3 and 4) never produce wait-states. They
   have a 8-bit ECC which avoids read-modify-write.
R/W
0x00000000
Address@intram7 : 0x000b8000
Address@intram7_mirror_sram : 0x200b8000
Address@intram7_mirror_ocp : 0x400b8000
Bits Reset value Name Description
31 - 0 0
intram7_base


intram7_end
(NETX_MEM_INTRN_SRAM7_END)
internal SRAM AHBL slave 7 end address
R/W
0x00000000
Address@intram7 : 0x000bfffc
Address@intram7_mirror_sram : 0x200bfffc
Address@intram7_mirror_ocp : 0x400bfffc
Bits Reset value Name Description
31 - 0 0
intram7_end



Base Address Area: sdram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sdram_base
1-3fffffe 4-ffffff8 -  reserved
3ffffff ffffffc R sdram_end

sdram_base
external SDRAM chip-select start address
Area size: 256MB
R/W
0x00000000
Address : 0x10000000
Bits Reset value Name Description
31 - 0 0
sdram_base


sdram_end
external SDRAM chip-select end address
R
Address : 0x1ffffffc
Bits Name Description
31 - 0 sdram_end



Base Address Area: extsram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W cs0_base
1-7ffffe 4-1fffff8 -  reserved
7fffff 1fffffc R cs0_end
800000 2000000 R/W cs1_base
800001-fffffe 2000004-3fffff8 -  reserved
ffffff 3fffffc R cs1_end
1000000 4000000 R/W cs2_base
1000001-17ffffe 4000004-5fffff8 -  reserved
17fffff 5fffffc R cs2_end
1800000 6000000 R/W cs3_base
1800001-1fffffe 6000004-7fffff8 -  reserved
1ffffff 7fffffc R cs3_end

cs0_base
external SRAM/Flash/NVRAM,... chip-select 0 start address
Area size: 32MB
R/W
0x00000000
Address : 0x68000000
Bits Reset value Name Description
31 - 0 0
cs0_base


cs0_end
external SRAM/Flash/NVRAM,... chip-select 0 end address
R
Address : 0x69fffffc
Bits Name Description
31 - 0 cs0_end


cs1_base
external SRAM/Flash/NVRAM,... chip-select 1 start address
Area size: 32MB
R/W
0x00000000
Address : 0x6a000000
Bits Reset value Name Description
31 - 0 0
cs1_base


cs1_end
external SRAM/Flash/NVRAM,... chip-select 1 end address
R
Address : 0x6bfffffc
Bits Name Description
31 - 0 cs1_end


cs2_base
external SRAM/Flash/NVRAM,... chip-select 2 start address
Area size: 32MB
R/W
0x00000000
Address : 0x6c000000
Bits Reset value Name Description
31 - 0 0
cs2_base


cs2_end
external SRAM/Flash/NVRAM,... chip-select 2 end address
R
Address : 0x6dfffffc
Bits Name Description
31 - 0 cs2_end


cs3_base
external SRAM/Flash/NVRAM,... chip-select 3 start address
Area size: 32MB
R/W
0x00000000
Address : 0x6e000000
Bits Reset value Name Description
31 - 0 0
cs3_base


cs3_end
external SRAM/Flash/NVRAM,... chip-select 3 end address
R
Address : 0x6ffffffc
Bits Name Description
31 - 0 cs3_end



Base Address Area: cm4_scs

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0-1 0-4 -  reserved
2 8 R/W cm4_scs_actlr
3 c -  reserved
4 10 R/W cm4_scs_stcsr
5 14 R/W cm4_scs_strvr
6 18 R/W cm4_scs_stcvr
7 1c R cm4_scs_stcr
8-3f 20-fc -  reserved
40 100 R/W cm4_scs_nvic_iser0
41 104 R/W cm4_scs_nvic_iser1
42 108 R/W cm4_scs_nvic_iser2
43-5f 10c-17c -  reserved
60 180 R/W cm4_scs_nvic_icer0
61 184 R/W cm4_scs_nvic_icer1
62 188 R/W cm4_scs_nvic_icer2
63-7f 18c-1fc -  reserved
80 200 R/W cm4_scs_nvic_ispr0
81 204 R/W cm4_scs_nvic_ispr1
82 208 R/W cm4_scs_nvic_ispr2
83-9f 20c-27c -  reserved
a0 280 R/W cm4_scs_nvic_icpr0
a1 284 R/W cm4_scs_nvic_icpr1
a2 288 R/W cm4_scs_nvic_icpr2
a3-bf 28c-2fc -  reserved
c0 300 R cm4_scs_nvic_iabr0
c1 304 R cm4_scs_nvic_iabr1
c2 308 R cm4_scs_nvic_iabr2
c3-ff 30c-3fc -  reserved
100 400 R/W cm4_scs_nvic_ipr0
101 404 R/W cm4_scs_nvic_ipr1
102 408 R/W cm4_scs_nvic_ipr2
103 40c R/W cm4_scs_nvic_ipr3
104 410 R/W cm4_scs_nvic_ipr4
105 414 R/W cm4_scs_nvic_ipr5
106 418 R/W cm4_scs_nvic_ipr6
107 41c R/W cm4_scs_nvic_ipr7
108 420 R/W cm4_scs_nvic_ipr8
109 424 R/W cm4_scs_nvic_ipr9
10a 428 R/W cm4_scs_nvic_ipr10
10b 42c R/W cm4_scs_nvic_ipr11
10c 430 R/W cm4_scs_nvic_ipr12
10d 434 R/W cm4_scs_nvic_ipr13
10e 438 R/W cm4_scs_nvic_ipr14
10f 43c R/W cm4_scs_nvic_ipr15
110 440 R/W cm4_scs_nvic_ipr16
111-33f 444-cfc -  reserved
340 d00 R cm4_scs_cpuid
341 d04 R/W cm4_scs_icsr
342 d08 R/W cm4_scs_vtor
343 d0c R/W cm4_scs_aircr
344 d10 R/W cm4_scs_scr
345 d14 R/W cm4_scs_ccr
346 d18 R/W cm4_scs_shpr1
347 d1c R/W cm4_scs_shpr2
348 d20 R/W cm4_scs_shpr3
349 d24 R/W cm4_scs_shcsr
34a d28 R/W cm4_scs_cfsr
34b d2c R/W cm4_scs_hfsr
34c d30 R/W cm4_scs_dfsr
34d d34 R/W cm4_scs_mmfar
34e d38 R/W cm4_scs_bfar
34f d3c R/W cm4_scs_afsr
350-361 d40-d84 -  reserved
362 d88 R/W cm4_scs_cpacr
363-37b d8c-dec -  reserved
37c df0 R/W cm4_scs_dhcsr
37d df4 W cm4_scs_dcrsr
37e df8 R/W cm4_scs_dcrdr
37f dfc R/W cm4_scs_demcr
380-3f3 e00-fcc -  reserved
3f4 fd0 R cm4_scs_pidr4
3f5-3f7 fd4-fdc -  reserved
3f8 fe0 R cm4_scs_pidr0
3f9 fe4 R cm4_scs_pidr1
3fa fe8 R cm4_scs_pidr2
3fb fec R cm4_scs_pidr3
3fc ff0 R cm4_scs_cidr0
3fd ff4 R cm4_scs_cidr1
3fe ff8 R cm4_scs_cidr2
3ff ffc R cm4_scs_cidr3

cm4_scs_actlr
Auxiliary control register
R/W
0x00000000
Address : 0xe000e008
Bits Reset value Name Description
31 - 0 0
cm4_scs_actlr


cm4_scs_stcsr
SysTick control and status register
R/W
0x00000000
Address : 0xe000e010
Bits Reset value Name Description
31 - 0 0
cm4_scs_stcsr


cm4_scs_strvr
SysTick Reload Value register
R/W
0x00000000
Address : 0xe000e014
Bits Reset value Name Description
31 - 0 0
cm4_scs_strvr


cm4_scs_stcvr
SysTick current value register
R/W
0x00000000
Address : 0xe000e018
Bits Reset value Name Description
31 - 0 0
cm4_scs_stcvr


cm4_scs_stcr
SysTick calibration value register
R
Address : 0xe000e01c
Bits Name Description
31 - 0 cm4_scs_stcr


cm4_scs_nvic_iser0
Interrupt set-enable register 0
Enables, or reads the enable state of a group of interrupts.
R/W
0x00000000
Address : 0xe000e100
Bits Reset value Name Description
31 - 0 0x0
setena
For register cm4_scs_nvic_iser[n], enables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, enable interrupt.
Software can enable multiple interrupts in a single write to cm4_scs_nvic_iser[n].


cm4_scs_nvic_iser1
Interrupt set-enable register 1
Enables, or reads the enable state of a group of interrupts.
R/W
0x00000000
Address : 0xe000e104
Bits Reset value Name Description
31 - 0 0x0
setena
For register cm4_scs_nvic_iser[n], enables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, enable interrupt.
Software can enable multiple interrupts in a single write to cm4_scs_nvic_iser[n].


cm4_scs_nvic_iser2
Interrupt set-enable register 2
Enables, or reads the enable state of a group of interrupts.
R/W
0x00000000
Address : 0xe000e108
Bits Reset value Name Description
31 - 0 0x0
setena
For register cm4_scs_nvic_iser[n], enables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, enable interrupt.
Software can enable multiple interrupts in a single write to cm4_scs_nvic_iser[n].


cm4_scs_nvic_icer0
Interrupt clear-enable register 0
Disables, or reads the enable state of a group of interrupts.
R/W
0x00000000
Address : 0xe000e180
Bits Reset value Name Description
31 - 0 0x0
clrena
For register cm4_scs_nvic_icer[n], disables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, disable interrupt.
Software can disable multiple interrupts in a single write to cm4_scs_nvic_icer[n].


cm4_scs_nvic_icer1
Interrupt clear-enable register 1
Disables, or reads the enable state of a group of interrupts.
R/W
0x00000000
Address : 0xe000e184
Bits Reset value Name Description
31 - 0 0x0
clrena
For register cm4_scs_nvic_icer[n], disables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, disable interrupt.
Software can disable multiple interrupts in a single write to cm4_scs_nvic_icer[n].


cm4_scs_nvic_icer2
Interrupt clear-enable register 2
Disables, or reads the enable state of a group of interrupts.
R/W
0x00000000
Address : 0xe000e188
Bits Reset value Name Description
31 - 0 0x0
clrena
For register cm4_scs_nvic_icer[n], disables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, disable interrupt.
Software can disable multiple interrupts in a single write to cm4_scs_nvic_icer[n].


cm4_scs_nvic_ispr0
Interrupt set-pending register 0
For a group of interrupts, changes interrupt status to pending, or shows the current pending status.
R/W
0x00000000
Address : 0xe000e200
Bits Reset value Name Description
31 - 0 0x0
setpend
For register cm4_scs_nvic_ispr[n], changes the state of interrupt (m+(32*n)) to pending, or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, change state of \
interrupt to pending.
Software can set multiple interrupts to pending state in a single write to cm4_scs_nvic_ispr[n].


cm4_scs_nvic_ispr1
Interrupt set-pending register 1
For a group of interrupts, changes interrupt status to pending, or shows the current pending status.
R/W
0x00000000
Address : 0xe000e204
Bits Reset value Name Description
31 - 0 0x0
setpend
For register cm4_scs_nvic_ispr[n], changes the state of interrupt (m+(32*n)) to pending, or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, change state of \
interrupt to pending.
Software can set multiple interrupts to pending state in a single write to cm4_scs_nvic_ispr[n].


cm4_scs_nvic_ispr2
Interrupt set-pending register 2
For a group of interrupts, changes interrupt status to pending, or shows the current pending status.
R/W
0x00000000
Address : 0xe000e208
Bits Reset value Name Description
31 - 0 0x0
setpend
For register cm4_scs_nvic_ispr[n], changes the state of interrupt (m+(32*n)) to pending, or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, change state of \
interrupt to pending.
Software can set multiple interrupts to pending state in a single write to cm4_scs_nvic_ispr[n].


cm4_scs_nvic_icpr0
Interrupt clear-pending register 0
For a group of interrupts, clears the interrupt pending status, or shows the current pending status.
R/W
0x00000000
Address : 0xe000e280
Bits Reset value Name Description
31 - 0 0x0
clrpend
For register cm4_scs_nvic_ispr[n], clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, clears the pending state of \
interrupt.
Software can clear the pending state of multiple interrupts in a single write to cm4_scs_nvic_icpr[n].


cm4_scs_nvic_icpr1
Interrupt clear-pending register 1
For a group of interrupts, clears the interrupt pending status, or shows the current pending status.
R/W
0x00000000
Address : 0xe000e284
Bits Reset value Name Description
31 - 0 0x0
clrpend
For register cm4_scs_nvic_ispr[n], clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, clears the pending state of \
interrupt.
Software can clear the pending state of multiple interrupts in a single write to cm4_scs_nvic_icpr[n].


cm4_scs_nvic_icpr2
Interrupt clear-pending register 2
For a group of interrupts, clears the interrupt pending status, or shows the current pending status.
R/W
0x00000000
Address : 0xe000e288
Bits Reset value Name Description
31 - 0 0x0
clrpend
For register cm4_scs_nvic_ispr[n], clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, clears the pending state of \
interrupt.
Software can clear the pending state of multiple interrupts in a single write to cm4_scs_nvic_icpr[n].


cm4_scs_nvic_iabr0
Interrupt active bit register 0
For a group of 32 interrupts, shows whether each interrupt is active.
R
Address : 0xe000e300
Bits Name Description
31 - 0 active
For register cm4_scs_nvic_iabr[n], shows whether interrupt (m+(32*n)) is active.


cm4_scs_nvic_iabr1
Interrupt active bit register 1
For a group of 32 interrupts, shows whether each interrupt is active.
R
Address : 0xe000e304
Bits Name Description
31 - 0 active
For register cm4_scs_nvic_iabr[n], shows whether interrupt (m+(32*n)) is active.


cm4_scs_nvic_iabr2
Interrupt active bit register 2
For a group of 32 interrupts, shows whether each interrupt is active.
R
Address : 0xe000e308
Bits Name Description
31 - 0 active
For register cm4_scs_nvic_iabr[n], shows whether interrupt (m+(32*n)) is active.


cm4_scs_nvic_ipr0
Interrupt priority register 0
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e400
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr1
Interrupt priority register 1
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e404
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr2
Interrupt priority register 2
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e408
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr3
Interrupt priority register 3
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e40c
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr4
Interrupt priority register 4
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e410
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr5
Interrupt priority register 5
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e414
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr6
Interrupt priority register 6
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e418
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr7
Interrupt priority register 7
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e41c
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr8
Interrupt priority register 8
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e420
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr9
Interrupt priority register 9
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e424
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr10
Interrupt priority register 10
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e428
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr11
Interrupt priority register 11
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e42c
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr12
Interrupt priority register 12
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e430
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr13
Interrupt priority register 13
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e434
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr14
Interrupt priority register 14
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e438
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr15
Interrupt priority register 15
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e43c
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_nvic_ipr16
Interrupt priority register 16
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e440
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm4_scs_nvic_ipr[n], priority of interrupt number 4n.


cm4_scs_cpuid
CPUID base register
R
Address : 0xe000ed00
Bits Name Description
31 - 0 cm4_scs_cpuid


cm4_scs_icsr
Interrupt control and state register
R/W
0x00000000
Address : 0xe000ed04
Bits Reset value Name Description
31 - 0 0
cm4_scs_icsr


cm4_scs_vtor
Vector table offset register
Holds the vector table address.
R/W
0x00000000
Address : 0xe000ed08
Bits Reset value Name Description
31 - 7 0x0
tbloff
Bits[31:7] of the vector table address.
6 - 0 0
-
 reserved


cm4_scs_aircr
Application interrupt and reset control reister
Sets or returns interrupt control data.
R/W
0xfa050000
Address : 0xe000ed0c
Bits Reset value Name Description
31 - 16 0xfa05
vectkey
Vector Key.
Register writes must write 0x05FA to this field, otherwise the write is ignored.
On reads, returns 0xFA05.
15 "0"
endianness
Indicates the memory system endianness: 0 - Little endian, 1 - Big endian.
This bit is static or configured by a hardware input on reset.
This bit is read only.
14 - 11 0
-
 reserved
10 - 8 "000"
prigroup
Priority grouping, indicates the binary point position.
7 - 3 0
-
 reserved
2 "0"
sysresetreq
System Reset Request.
Writing 1 to this bit asserts a signal to the external system to request a Local reset. A Local or Power-on reset clears this bit to 0.
1 "0"
vectclractive
Writing 1 to this bit clears all active state information for fixed and configurable exceptions. This includes clearing the IPSR to zero.
The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE.
This bit is write only.
0 "0"
vectreset
Writing 1 to this bit causes a local system reset. This bit self-clears.
The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE.
When the processor is halted in Debug state, if a write to the register writes a 1 to both VECTRESET and SYSRESETREQ, the behavior is UNPREDICTABLE.
This bit is write only.
Note: The netx90 doesn't support a local system reset. Writing 1 results in UNPREDICTABLE behaviour of the whole system! Use sysresetreq instead!


cm4_scs_scr
System control Register
R/W
0x00000000
Address : 0xe000ed10
Bits Reset value Name Description
31 - 0 0
cm4_scs_scr


cm4_scs_ccr
Configuration and control Register
R/W
0x00000000
Address : 0xe000ed14
Bits Reset value Name Description
31 - 0 0
cm4_scs_ccr


cm4_scs_shpr1
System Handler Priority Register 1
R/W
0x00000000
Address : 0xe000ed18
Bits Reset value Name Description
31 - 0 0
cm4_scs_shpr1


cm4_scs_shpr2
System Handler Priority Register 2
R/W
0x00000000
Address : 0xe000ed1c
Bits Reset value Name Description
31 - 0 0
cm4_scs_shpr2


cm4_scs_shpr3
System Handler Priority Register 3
R/W
0x00000000
Address : 0xe000ed20
Bits Reset value Name Description
31 - 0 0
cm4_scs_shpr3


cm4_scs_shcsr
System Handler Control and State Register
R/W
0x00000000
Address : 0xe000ed24
Bits Reset value Name Description
31 - 0 0
cm4_scs_shcsr


cm4_scs_cfsr
Configurable Fault Status Register
Contains the three Configurable Fault Status Registers.
R/W
0x00000000
Address : 0xe000ed28
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
ufsr_divbyzero
Divide by zero error has occurred.
24 "0"
ufsr_unaligned
Unaligned access error has occurred.
Multi-word accesses always fault if not word aligned. Software can configure unaligned word and halfword accesses to fault, by enabling UNALIGN_TRP in the CCR.
23 - 20 0
-
 reserved
19 "0"
ufsr_nocp
A coprocessor access error has occurred. This shows that the coprocessor is disabled or not present.
18 "0"
ufsr_invpc
An integrity check error has occurred on EXC_RETURN.
17 "0"
ufsr_invstate
Instruction executed with invalid EPSR.T or EPSR.IT field.
16 "0"
ufsr_undefinstr
The processor has attempted to execute an undefined instruction. This might be an undefined instruction associated with an enabled coprocessor.
15 "0"
bfsr_bfarvalid
BFAR has valid contents.
14 0
-
 reserved
13 "0"
bfsr_lsperr
A bus fault occurred during FP lazy state preservation.
12 "0"
bfsr_stkerr
A derived bus fault has occurred on exception entry.
11 "0"
bfsr_unstkerr
A derived bus fault has occurred on exception return.
10 "0"
bfsr_impreciserr
Imprecise data access error has occurred.
9 "0"
bfsr_preciserr
A precise data access error has occurred, and the processor has written the faulting address to the BFAR.
8 "0"
bfsr_ibuserr
A bus fault on an instruction prefetch has occurred. The fault is signaled only if the instruction is issued.
7 "0"
mmfsr_mmarvalid
MMFAR has valid contents.
6 0
-
 reserved
5 "0"
mmfsr_lsperr
A MemManage fault occurred during FP lazy state preservation.
4 "0"
mmfsr_mstkerr
A derived MemManage fault occurred on exception entry.
3 "0"
mmfsr_munstkerr
A derived MemManage fault occurred on exception return.
2 0
-
 reserved
1 "0"
mmfsr_daccviol
Data access violation. The MMFAR shows the data address that the load or store tried to access.
0 "0"
mmfsr_iaccviol
MPU or Execute Never (XN) default memory map access violation on an instruction fetch has occurred. The fault is signalled only if the instruction is issued.


cm4_scs_hfsr
HardFault Status Register
R/W
0x00000000
Address : 0xe000ed2c
Bits Reset value Name Description
31 - 0 0
cm4_scs_hfsr


cm4_scs_dfsr
Debug fault status Register
Shows which debug event occurred.
Note: Writing 1 to a register bit clears the bit to 0.
R/W
0x00000000
Address : 0xe000ed30
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
external
Indicates a debug event generated because of the assertion of an external debug request.
3 "0"
vcatch
Indicates triggering of a Vector catch.
2 "0"
dwttrap
Indicates a debug event generated by the DWT.
1 "0"
bkpt
Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB.
0 "0"
halted
Indicates a debug event generated by either:
- A C_HALT or C_STEP request, triggered by a write to the DHCSR.
- A step request triggered by setting DEMCR.MON_STEP to 1.


cm4_scs_mmfar
MemManage Faul Address Register
R/W
0x00000000
Address : 0xe000ed34
Bits Reset value Name Description
31 - 0 0
cm4_scs_mmfar


cm4_scs_bfar
BusFault Address Register
R/W
0x00000000
Address : 0xe000ed38
Bits Reset value Name Description
31 - 0 0
cm4_scs_bfar


cm4_scs_afsr
Auxiliary Fault Status Register
R/W
0x00000000
Address : 0xe000ed3c
Bits Reset value Name Description
31 - 0 0
cm4_scs_afsr


cm4_scs_cpacr
Coprocessor Access Control Register
R/W
0x00000000
Address : 0xe000ed88
Bits Reset value Name Description
31 - 0 0
cm4_scs_cpacr


cm4_scs_dhcsr
Debug halting control and status register
Controls halting debug.
Note: On writes bits 31-16 (dbgkey) must be set to 0xA05F.
R/W
0x00000000
Address : 0xe000edf0
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
s_reset_st
Indicates whether the processor has been reset since the last read of DHCSR.
This is a sticky bit, that clears to 0 on a read of DHCSR. This bit is read-only.
24 "0"
s_retire_st
Set to 1 every time the processor retires one or more instructions.
This is a sticky bit, that clears to 0 on a read of DHCSR.
The architecture does not define precisely when this bit is set to 1. It requires only that this happen periodically in Non-debug state to indicate that software execution is progressing.
This bit is UNKNOWN after a Power-on or Local reset, but then is set to 1 as soon as the processor executes and retires an instruction.
This bit is read-only.
23 - 20 0
-
 reserved
19 "0"
s_lockup
Indicates whether the processor is locked up because of an unrecoverable exception.
This bit can only be read as 1 by a remote debugger, using the DAP. The value of 1 indicates that the processor is running but locked up.
The bit clears to 0 when the processor enters Debug state.
This bit is read-only.
18 "0"
s_sleep
Indicates whether the processor is sleeping.
The debugger must set the C_HALT bit to 1 to gain control, or wait for an interrupt or other wakeup event to wakeup the system.
This bit is read-only.
17 "0"
s_halt
Indicates whether the processor is in Debug state.
This bit is read-only.
16 "0"
s_regrdy
A handshake flag for transfers through the DCRDR:
- Writing to DCRSR clears the bit to 0.
- Completion of the DCRDR transfer then sets the bit to 1.
For more information about DCRDR transfers see Debug Core Register Data Register, DCRDR.
This bit is valid only when the processor is in Debug state, otherwise the bit is UNKNOWN.
This bit is read-only.
15 - 6 0
-
 reserved
5 "0"
c_snapstall
Allow imprecise entry to Debug state. The actions on writing to this bit are:
- 0: No action.
- 1: Allow imprecise entry to Debug state, for example by forcing any stalled load \
or store instruction to complete.
Setting this bit to 1 allows a debugger to request imprecise entry to Debug state.
The effect of setting this bit to 1 is UNPREDICTABLE unless the DHCSR write also sets C_DEBUGEN and C_HALT to 1. This means that if the processor is not already in Debug stateit enters Debug state when the stalled instruction completes.
Writing 1 to this bit makes the state of the memory system UNPREDICTABLE. Therefore, if a debugger writes 1 to this bit it must reset the processor before leaving Debug state.
Note:
- A debugger can write to the DHCSR to clear this bit to 0. However, this does not remove the UNPREDICTABLE state of the memory system caused by setting C_SNAPSTALL to 1.
- The architecture does not guarantee that setting this bit to 1 will force entry to Debug state.
- ARM strongly recommends that a value of 1 is never written to C_SNAPSTALL when the processor is in Debug state.
4 0
-
 reserved
3 "0"
c_maskints
When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts:
- 0: Do not mask.
- 1: Mask PendSV, SysTick and external configurable interrupts.
The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both:
- Before the write to DHCSR, the value of the C_HALT bit is 1.
- The write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit.
This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit.
The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN.
This bit is UNKNOWN after a Power-on reset.
2 "0"
c_step
Processor step bit. The effects of writes to this bit are:
- 0: No effect.
- 1: Single step enabled.
This bit is UNKNOWN after a Power-on reset.
1 "0"
c_halt
Processor halt bit. The effects of writes to this bit are:
- 0: Causes the processor to leave Debug state, if in Debug state.
- 1: Halt the processor.
This bit is UNKNOWN after a Power-on reset, and is 0 after a Local reset.
0 "0"
c_debugen
Halting debug enable bit.
If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.
This bit can only be written by the DAP, it ignores writes from software.


cm4_scs_dcrsr
Debug core register selector register
With the DCRDR, the DCRSR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension registers. A write to DCRSR specifies the register to transfer, whether the transfer is a read or a write, and starts the transfer.
W
0x00000000
Address : 0xe000edf4
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 "0"
regwnr
Specifies the access type for the transfer:
0 : Read.
1 : Write.
15 - 7 0
-
 reserved
6 - 0 "0000000"
regsel
Specifies the ARM core register, special-purpose register, or Floating-point extension register, to transfer:
 0 - 12  ARM core registers R0-R12.
     13  The current SP. See also values 17 (MSP) and 18 (PSP).
     14  LR.
     15  DebugReturnAddress.
     16  xPSR.
     17  Main stack pointer, MSP.
     18  Process stack pointer, PSP.
     20
 Bits[31:24]: CONTROL, Bits[23:16]: FAULTMASK, Bits[15:8]: BASEPRI, Bits[7:0]: PRIMASK.  In each field, the valid bits are packed with leading zeros. For example,  FAULTMASK is always a single bit, DCRDR[16], and DCRDR[23:17] is 0.
     33  Floating-point Status and Control Register, FPSCR.
 64 - 95  FP registers S0-S31.
All other values are Reserved.
If the processor does not implement the FP extension the REGSEL field is bits[4:0], and bits[6:5] are Reserved, SBZ.


cm4_scs_dcrdr
Debug core register data register
With the DCRSR, the DCRDR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension registers. The DCRDR is the data register for these accesses.
Used on its own, the DCRDR provides a message passing resource between an external debugger and a debug agent running on the processor.
Note: The architecture does not define any handshaking mechanism for this use of DCRDR.
R/W
0x00000000
Address : 0xe000edf8
Bits Reset value Name Description
31 - 0 0x0
dbgtmp
Data temporary cache, for reading and writing the ARM core registers, special-purpose registers, and Floating-point extension registers.


cm4_scs_demcr
Debug exception and monitor control register
Manages vector catch behavior and DebugMonitor handling when debugging.
R/W
0x00000000
Address : 0xe000edfc
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
trcena
Global enable for all DWT and ITM features:
- 0: DWT and ITM units disabled.
- 1: DWT and ITM units enabled.
If the DWT and ITM units are not implemented, this bit is UNK/SBZP.
When TRCENA is set to 0:
- DWT registers return UNKNOWN values on reads. Whether the processor ignores writes to the DWT unit is IMPLEMENTATION DEFINED.
- ITM registers return UNKNOWN values on reads. Whether the processor ignores writes to the ITM unit is IMPLEMENTATION DEFINED.
Setting this bit to 0 might not stop all events. To ensure all events are stopped, software must set all DWT and ITM feature enable bits to 0, and then set this bit to 0.
23 - 20 0
-
 reserved
19 "0"
mon_req
DebugMonitor semaphore bit. The processor does not use this bit. The monitor software defines the meaning and use of this bit.
18 "0"
mon_step
When MON_EN is set to 0, this feature is disabled and the processor ignores MON_STEP.
When MON_EN is set to 1, the meaning of MON_STEP is:
- 0: Do not step the processor.
- 1: Step the processor.
Setting this bit to 1 makes the step request pending.
The effect of changing this bit at an execution priority that is lower than the priority of the DebugMonitor exception is UNPREDICTABLE.
17 "0"
mon_pend
Sets or clears the pending state of the DebugMonitor exception:
- 0: Clear the status of the DebugMonitor exception to not pending.
- 1: Set the status of the DebugMonitor exception to pending.
When the DebugMonitor exception is pending it becomes active subject to the exception priority rules. A debugger can use this bit to wakeup the monitor using the DAP.
The effect of setting this bit to 1 is not affected by the value of the MON_EN bit. A debugger can set MON_PEND to 1, and force the processor to take a DebugMonitor exception, even when MON_EN is set to 0.
16 "0"
mon_en
Enable the DebugMonitor exception.
If DHCSR.C_DEBUGEN is set to 1, the processor ignores the value of this bit.
15 - 11 0
-
 reserved
10 "0"
vc_harderr
Enable halting debug trap on a HardFault exception.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
9 "0"
vc_interr
Enable halting debug trap on a fault occurring during exception entry or exception return.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
8 "0"
vc_buserr
Enable halting debug trap on a BusFault exception.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
7 "0"
vc_staterr
Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
6 "0"
vc_chkerr
Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
5 "0"
vc_nocperr
Enable halting debug trap on a UsageFault caused by an access to a Coprocessor.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
4 "0"
vc_mmerr
Enable halting debug trap on a MemManage exception.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
3 - 1 0
-
 reserved
0 "0"
vc_corereset
Enable Reset Vector Catch. This causes a Local reset to halt a running system.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.


cm4_scs_pidr4
Peripheral ID Register 4
R
Address : 0xe000efd0
Bits Name Description
31 - 0 cm4_scs_pidr4


cm4_scs_pidr0
Peripheral ID Register 0
R
Address : 0xe000efe0
Bits Name Description
31 - 0 cm4_scs_pidr0


cm4_scs_pidr1
Peripheral ID Register 1
R
Address : 0xe000efe4
Bits Name Description
31 - 0 cm4_scs_pidr1


cm4_scs_pidr2
Peripheral ID Register 2
R
Address : 0xe000efe8
Bits Name Description
31 - 0 cm4_scs_pidr2


cm4_scs_pidr3
Peripheral ID Register 3
R
Address : 0xe000efec
Bits Name Description
31 - 0 cm4_scs_pidr3


cm4_scs_cidr0
Component ID Register 0
R
Address : 0xe000eff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble byte 0.


cm4_scs_cidr1
Component ID Register 1
R
Address : 0xe000eff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Component class.
3 - 0 prmbl_1
Preamble bits[11:8].


cm4_scs_cidr2
Component ID Register 2
R
Address : 0xe000eff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble byte 2.


cm4_scs_cidr3
Component ID Register 3
R
Address : 0xe000effc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble byte 3.



Base Address Area: cm4_misc_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R cm4_misc_ctrl_cpu_info
1 4 R/W cm4_misc_ctrl_fpu_irq_raw
2 8 R cm4_misc_ctrl_fpu_irq_masked
3 c R/W cm4_misc_ctrl_fpu_irq_msk_set
4 10 R/W cm4_misc_ctrl_fpu_irq_msk_reset
5-3ff 14-ffc -  reserved

cm4_misc_ctrl_cpu_info
CPU information register
Provides a processor identification mechanism to distinguish between Com ARM and App ARM.
R
Address : 0xe0043000
Bits Name Description
31 - 2 -
 reserved
1 fpu
CPU has FPU
If '0' all cm4_misc_ctrl_fpu_* registers have no effect and are read as zero.
0 id
CPU identification
0: Com ARM
1: App ARM


cm4_misc_ctrl_fpu_irq_raw
FPU raw IRQ
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
Note: Before clearing an IRQ in this register, the corresponding exception status must be cleared within the FPU. Otherwise
the IRQ will be re-asserted immediately.
R/W
0x00000000
Address : 0xe0043004
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
idc
Input denormal (ARM-specific exception).
4 "0"
ioc
Invalid operation (IEEE 754-2008 defined exception).
3 "0"
dzc
Division by zero (IEEE 754-2008 defined exception).
2 "0"
ofc
Overflow (IEEE 754-2008 defined exception).
1 "0"
ufc
Underflow (IEEE 754-2008 defined exception).
0 "0"
ixc
Inexact (IEEE 754-2008 defined exception).


cm4_misc_ctrl_fpu_irq_masked
FPU masked IRQ
Shows status of masked IRQs.
R
Address : 0xe0043008
Bits Name Description
31 - 6 -
 reserved
5 idc
Input denormal (ARM-specific exception).
4 ioc
Invalid operation (IEEE 754-2008 defined exception).
3 dzc
Division by zero (IEEE 754-2008 defined exception).
2 ofc
Overflow (IEEE 754-2008 defined exception).
1 ufc
Underflow (IEEE 754-2008 defined exception).
0 ixc
Inexact (IEEE 754-2008 defined exception).


cm4_misc_ctrl_fpu_irq_msk_set
FPU IRQ mask set
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to cm4_misc_ctrl_fpu_irq_raw.
R/W
0x00000000
Address : 0xe004300c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
idc
Input denormal (ARM-specific exception).
4 "0"
ioc
Invalid operation (IEEE 754-2008 defined exception).
3 "0"
dzc
Division by zero (IEEE 754-2008 defined exception).
2 "0"
ofc
Overflow (IEEE 754-2008 defined exception).
1 "0"
ufc
Underflow (IEEE 754-2008 defined exception).
0 "0"
ixc
Inexact (IEEE 754-2008 defined exception).


cm4_misc_ctrl_fpu_irq_msk_reset
FPU IRQ mask reset
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address : 0xe0043010
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
idc
Input denormal (ARM-specific exception).
4 "0"
ioc
Invalid operation (IEEE 754-2008 defined exception).
3 "0"
dzc
Division by zero (IEEE 754-2008 defined exception).
2 "0"
ofc
Overflow (IEEE 754-2008 defined exception).
1 "0"
ufc
Underflow (IEEE 754-2008 defined exception).
0 "0"
ixc
Inexact (IEEE 754-2008 defined exception).



Base Address Area: idpm_com

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W idpm_cfg0x0
1-3 4-c -  reserved
4 10 R/W idpm_addr_cfg
5-6 14-18 -  reserved
7 1c R idpm_status
8-d 20-34 -  reserved
e 38 R/W idpm_tunnel_cfg
f 3c R/W idpm_itbaddr
10 40 R/W idpm_win1_end
11 44 R/W idpm_win1_map
12 48 R/W idpm_win2_end
13 4c R/W idpm_win2_map
14 50 R/W idpm_win3_end
15 54 R/W idpm_win3_map
16 58 R/W idpm_win4_end
17 5c R/W idpm_win4_map
18-1f 60-7c -  reserved
20 80 R idpm_irq_raw
21 84 R/W idpm_irq_host_mask_set
22 88 R/W idpm_irq_host_mask_reset
23 8c R idpm_irq_host_masked
24-2f 90-bc -  reserved
30 c0 R/W idpm_sw_irq
31-35 c4-d4 -  reserved
36 d8 R/W idpm_sys_sta
37 dc R/W idpm_reset_request
38 e0 R/W idpm_firmware_irq_raw
39-3b e4-ec -  reserved
3c f0 R/W idpm_firmware_irq_mask
3d-3e f4-f8 -  reserved
3f fc R idpm_netx_version

idpm_cfg0x0
DPM IO Control Register 0.
This register is accessible in any DPM-mode (8, 16, 32 bit, SRAM, Intel, Motorola, little endian, big endian) by access to DPM address 0.
Basic DPM settings are configurable here to make higher addresses accessible.
To avoid instable system configurations, global changes of important configuration registers must be confirmed
(re)writing 'mode' bit field of this register. View 'mode' description for details.
R/W
0x00000000
Address : 0xff001b00
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 4 "00"
endian
Endianess of 32 bit (DWord) address alignment (B0: least significant byte, B3: most significant byte):
coding   Address   A+3   A+2   A+1   A+0
  00   little endian   B3   B2   B1   B0
  01   16 bit big endian   B2   B3   B0   B1
  10   32 bit big endian   B0   B1   B2   B3
  11   reserved        
Little endian is used netX inside. If big endian host device is used, set to this 01 or 10 according to
host device data width.
3 - 1 0
-
 reserved
0 "0"
enable
Global IDPM enable bit.
The IDPM module must be enabled by the INTLOGIC area before the host area (i.e. DPM mirrors of INTRAMHS) can be used.
While disabled all host access (access to DPM mirrors of INTRAMHS) will be ignored. Read will return 0x0bad0bad.


idpm_addr_cfg
DPM External Address Configuration Register.
R/W
0x00000000
Address : 0xff001b10
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 4 "00"
cfg_win_addr_cfg
Location of the DPM Configuration Window (Window 0).
Supported settings are:
 00: Low Configuration Window: The Configuration Window is located in the first 256 bytes of external DPM address
range (0x0 to 0xff). It is located before the first enabled Data Window (1 to 4).
 01: High Configuration Window: The Configuration Window is located in the last 256 bytes of external DPM address
range.
     Example: 'addr_range' is 8kB: Configuration Window is located in 0x1F00..0x1FFF.
 10: reserved.
 11: Configuration Window is disabled for external DPM access. Full DPM address
range can be used for Windows 1 to 4.
Note:
  The Configuration Window 0 has higher priority than normal DPM Window. The location of the Configuration Window
  does not depend on the Data Window configuration (the setting of the 'dpm_winX_end' or 'dpm_winX_map' registers).
  I.e. for setting '00' (low Configuration Window) the first enabled Data Window starts at address 0x100. For
  setting '01' (high Configuration Window) it would hide the last 256 bytes of the last enabled Data Window when
  this is configured to end on the last external address.
  The Configuration Window 0 has lower priority than Access Tunnel. I.e. the Access Tunnel could be laid over
  the configuration window.
3 - 0 0
-
 reserved


idpm_status
DPM Status Register.
R
Address : 0xff001b1c
Bits Name Description
31 - 1 -
 reserved
0 unlocked
DPM is locked during netX power up and boot phase.
DPM access to other addresses than DPM configuration window 0 cannot be done before this bit is
set to 1. Write access to data windows (netX AHB area) will be ignored and read access
will deliver invalid data while locked.
Poll for 1 after power-up or reset.


idpm_tunnel_cfg
DPM Access Tunnel Configuration Register.
The DPM Access Tunnel (DATunnel) is a 64 byte (16DWord) address window which can be mapped on any 64 byte boundary of the external
visible address space. At the last DWord (offset 0x3C) of the DATunnel the Internal Target Base Address (ITBAddr) can be programmed.
This is the base address of the 64 byte tunnel target area inside the full 32-bit netX address range (however some address areas
could not be reachable as connections could be cut from the DPM inside the netX dataswitch, refer to the dataswitch documentation
of your netX).
By the DWords 0 to 14 of the tunnel the internal netX addresses starting at ITBAddr can be reached. The 'enable'-bit must be active
for this (read-only functionality can be configured by 'wp_data'-bit).
For access to netX data with ITBAddr DWord offset 15, the lower bits 5 to 2 of the programmed ITBAddr are interpreted as a mapping
value. This value will be added to the internal access address before tunneling (wrapping around at the 64 byte boundary). Hence it
is possible to access always 15 of the 16 netX DWord while the one hidden by the ITBAddr can be selected by an appropriate mapping
value.
The ITBAddr can also be programmed by the 'idpm_itbaddr' register of the configuration window 0 (or the INTLOGIC area). The ITBAddr on
tunnel offset 0x3C can be write-protected by the 'wp_itbaddr'-bit. This could be useful to protect the NETX from reconfiguring the
tunnel from the host side but provides the host the internal NETX destination address anyhow. However this only makes sense when
the configuration window 0 is disabled ('idpm_addr_cfg' register). Otherwise the host could reconfigure the tunnel by the 'idpm_itbaddr'
register.
Additionally the 'tunnel_all'-bit provides the possibility of tunneling all 16DWords to the NETX side.
To protect the NETX from reconfiguring the tunnel from the host side when the configuration window 0 is enabled, the 'wp_cfg_win'
can be activated. Then the tunnel configuration can only be changed from the NETX side (INTLOGIC area) but not from configuration
window 0 (in contrast to the 'wp_itbaddr'-bit which protects only offset 0x3C).

External to internal address mapping for DATunnel area can be calculated by following formula:
   INAAdr = (ITBAddr & 0xffffffc0) + ((EDAAdr + ITBAddr) & 0x3C)

With:
   INAAdr: Internal netX Access Address
   ITBAddr: Internal netX 32-bit Tunnel Target Base Address
   EDAAdr: External DPM Access Address

Condition for DATunnel access is:
   EDAAdr>>6 equals value of bit field 'base' from this register.

To map netX internal DWord N to invisible last external DWord (15), use mapping value
   map = (N - 15) & 0xf
on bits 5 to 2.
Internal to external address offset inside DATunnel area for internal DWord N can be calculated by following formula:
   External offset = (N*4 - map*4) & 0x3C = (N*4 - ITBAddr) & 0x3C

Example 1:
   Access to netX sys_time module by host via DATunnel on external DPM addresses are starting at 0x240.
   - Set bit field 'base' of this register to 9 (0x240>>6), set 'enable'-bit (and write protection depending on application).
     DATunnel now is enabled on external DPM addresses 0x240 to 0x27f.
   - ITBAddr of netX4000 sys_time module is 0xf409c180.
     For direct DATunnel to this address, host must write 0xf409c180 to external DPM address 0x27c. This
     can be done e.g. by four byte accesses to 0x27c, 0x27d, 0x27e and 0x27f or by two 16-bit accesses to 0x27c and 0x27e.
     Now sys_time module registers 0 to 14 can be accessed on external DPM address 0x240 to 0x27b.

Example 2:
   Register 15 of sys_time is hidden by ITBAddr configuration on 0x27c in example 1 but must also be accessed. However, sys_time
   Register 6 is never kind of interest.
   - Configure this register like described in example 1.
   - To map Register 6 (Module offset 6*4) to external offset 0x3C (hidden data on DWord 15),
     the following rule must be complied:
        0x3C + map*4 = 6*4.
     That leads to a mapping value of:
        map*4 = (6*4 - 0x3C) & 0x3C = 1C
     Hence, write 0x101c101C to DATunnel DWord 15 (external DPM address 0x27c) to map sys_time Register 6 to
     hidden DWord 15.
     INAAdr now will be derived from EDAAdr before tunneling as follows:
        INAAdr = 0xf409c180 + ((EDAAdr + 0x1C) & 0x3C)
     External offset of Module DWord N results from:
        External offset = (N*4 - 0x1C) & 0x3C
     Register 15 of sys_time unit now can be accessed by external DPM address 0x240+((0xf*4-0x1C) & 0x3C) = 0x260 (i.e. Tunnel DWord 8).
     Register 0  of sys_time unit now can be accessed by external DPM address 0x240+((0x0*4-0x1C) & 0x3C) = 0x264 (i.e. Tunnel DWord 9).
     Register 1  of sys_time unit now can be accessed by external DPM address 0x240+((0x1*4-0x1C) & 0x3C) = 0x268 (i.e. Tunnel DWord 10).
     and so on.
     Register 6  of sys_time unit can not be accessed as it is hidden by ITBAddr configuration on 0x27c (i.e. Tunnel DWord 15).
     Register 7  of sys_time unit now can be accessed by external DPM address 0x240+((0x7*4-0x1C) & 0x3C) = 0x240 (i.e. Tunnel DWord 0).

Note:
  The IDPM tunnel is capable to target the INTRAMHS-memory associated to the IDPM and additionally the INTLOGIC_SYS
  area (addresses 0xf4080000 to 0xf80fffff, e.g. for SYSTIME). Other address areas can not be reached even when ITBAddr
  is configured for it. Write access to non-reachable addresses will be ignored, read access will deliver invalid data.

Attention:
  The IDPM tunnel could bypass the AHB firewalls. Example:
  The INTLOGIC_SYS firewall is configured to deny CA9 accesses while the CA9 is permitted for the INTRAMHS0 firewall. However, when
  the tunnel is programmed to target the INTLOGIC_SYS area the CA9 can reach it as the initial access (before tunnel remapping) is
  handled by the INTRAMHS0 firewall and not by the INTLOGIC_SYS firewall. To avoid abuse the 'tunnel_all' or the 'wp_itbaddr' bit
  and the 'wp_cfg_win' must be enabled. Then the tunnel e.g. can be used to access the SYSTIME registers but it cannot be reconfigured
  by the CA9 for abuse to other addresses.

Note:
  Configuration Window 0 access detection has higher priority than normal DPM Window
  detection but lower priority than Access Tunnel access detection.
R/W
0x00000101
Address : 0xff001b38
Bits Reset value Name Description
31 "0"
wp_cfg_win
Write-protect tunnel configuration inside the configuration window 0.
0: The two tunnel configuration registers ('idpm_tunnel_cfg' and 'idpm_itbaddr') can be programmed
via configuration window 0 and the INTLOGIC_SYS-IDPM address area.
1:
The tunnel configuration registers ('idpm_tunnel_cfg' and 'idpm_itbaddr') cannot
be programmed by the host via configuration window 0 (they are read-only for the host there).
They can only be programmed via the INTLOGIC_SYS-IDPM address area.
Note: Set this bit to protect the NETX from reconfiguring the tunnel by the host when configuration
   window 0 is activated for the host (e.g. for IRQ handling).
30 - 15 0
-
 reserved
14 - 6 0x4
base
DPM Access Tunnel (DATunnel) Base Address divided by 64 on external visible address space.
Note:
   Default setting for tunnel base is starting on external address 0x100.
5 - 4 0
-
 reserved
3 "0"
tunnel_all
Enable/disable the ITBAddr configuration register at tunnel offset 0x3C.
0: Only 15 DWords are tunneled to the internal tunnel target. The idpm_itbaddr is available at offset 0x3C.
One DWord of the tunnel target area is hidden by idpm_itbaddr.
1: All 16 DWords are tunneled to the internal tunnel target. The idpm_itbaddr is not available at offset 0x3C.
All 64 tunnel target bytes can be reached (no hidden register).
Note: Target mapping (base and map) will not be affected by this bit. Using a 'map' value not equal 0
   will always rotate the tunnel target addresses.
2 "0"
enable
Enable/disable Access Tunnel function.
1 "0"
wp_itbaddr
ITBAddr is write-protected from host.
0: The ITBAddr is mirrored to offset 0x3C of the tunnel and can also be programmed there.
1: ITBAddr (Internal netX 32 bit Tunnel Target Base Address) is read-only for tunnel offset 0x3C. It can only
be changed via configuration window 0 idpm_itbaddr address or the INTLOGIC IDPM area.
0 "1"
wp_data
Access Tunnel function is write-protected for data access (DWords 0 to 14 (15 for 'tunnel_all') of DATunnel).
0: Write access is forwarded through the tunnel.
1: Write access to DWords 0 to 14 (15 for 'tunnel_all') of DATunnel will be ignored.
Data write protection for host is enabled by default and can be disabled by clearing this bit.


idpm_itbaddr
DPM Access Tunnel (DATunnel) netX Internal Target Base Address (ITBAddr) Configuration Register.
For DPM Access Tunnel (DATunnel) function view description of dpm_tunnel_cfg register.
This register contains ITBAddr value that can also be changed by host on last offset 0x3c (last DWord) of
external DATunnel area (defined by bit field 'base' in 'dpm_tunnel_cfg' register). However this register can
also be write-protected from host if bit 'wp_itbaddr' in 'dpm_tunnel_cfg' register is set.
Write protection bits of DATunnel configured in 'dpm_tunnel_cfg' register can also be read from this register. Host
can read access rights from these bits on last DWord of external DATunnel address area.

Note: This register can be write-protected by the 'wp_cfg_win' and the 'wp_itbaddr'-bit of the 'idpm_tunnel_cfg' register.
R/W
0x00000001
Address : 0xff001b3c
Bits Reset value Name Description
31 - 6 0x0
base
Internal netX Tunnel Target Base Address (ITBAddr) divided by 64.
View description of dpm_tunnel_cfg register.
5 - 2 "0000"
map
Mapping part of ITBAddr.
View description of dpm_tunnel_cfg register.
1 "0"
wp_itbaddr_ro
ITBAddr is write-protected from host.
This is a read-only bit here. Its setting can be changed in 'dpm_tunnel_cfg' register.
View description of dpm_tunnel_cfg register.
0 "1"
wp_data_ro
Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel).
This is a read-only bit here. Its setting can be changed in 'dpm_tunnel_cfg' register.
View description of dpm_tunnel_cfg register.


idpm_win1_end
DPM Window 1 End Address Configuration Register.
Smallest DPM window configuration unit is 128 bytes (i.e. lowest 7 bits of address configuration are always 0).
At address 0x0 DPM configuration window is mapped after reset (length: 256 bytes, containing all DPM addresses defined here). Each window starts at
window end address of the preceding window. Hence external window 1 start address is 0x100, window 2 starts at value programmed in this register and so on.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.

Note:
  Configuration Window 0 access detection has higher priority than normal DPM Window
  detection but lower priority than Access Tunnel access detection.
R/W
0x00000000
Address : 0xff001b40
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 7 0x0
win_end
Window 1 End Address divided by 128.
Last external address is win_end*128-1.
Setting win_end to 0 will disable this window.
6 - 0 0
-
 reserved


idpm_win1_map
DPM Window 1 Address Map Configuration Register.
Smallest DPM window configuration unit is 128 bytes (i.e. lowest 7 bits of address configuration are always 0).
For further information view description of 'dpm_win1_end' register.
R/W
0x00000000
Address : 0xff001b44
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 - 7 "00000000"
win_map
Window 1 Address Mapping.
Internal access address HADDR to netX logic is combined by DPM interface by:
HADDR[31:16]: unchanged, as it comes form accessing master
HADDR[15:0]:  mapped DPM address. This part of address is defined by programmed win_map value for each window.
The value to be programmed is address bits 15 to 0 of netX internal window start address minus start address of the
external window (i.e. end address of preceding window) .
Example:
   Window n starts at 0x400 of external DPM address range (i.e. programmed win_end value of window (n-1) and targets
   netX address 0x05218000.
   For address calculation only lower 16 bits of netX address are relevant, i.e. 0x8000.
   The complete 16 bit address map value is then:0x8000-0x400=0x7C00.
   Hence the programmed 9 bit value must be 0x7C00>>7=0xf8.
6 0
-
 reserved
5 "0"
wp_cfg_win
Write-protect window configuration inside the configuration window 0.
0: All 8 window configuration registers ('dpm_winX_and' and 'dpm_winX_map') can be programmed
via configuration window 0 and the INTLOGIC-DPM address area.
1:
All 8 window configuration registers ('dpm_winX_and' and 'dpm_winX_map') cannot
be programmed by the host via configuration window 0 (they are read-only for the host there).
They can only be programmed via the INTLOGIC-DPM address area.
Note: Set this bit to protect the NETX from reconfiguring the window mapping by the host when configuration
   window 0 is activated for the host (e.g. for IRQ handling).
Note:
   To protect the netX completely from host-access to not permitted address areas it must be ensured that also
   the remapping of the DPM tunne cannot be changed by the host (refer to register 'dpm_tunnel_cfg').
Note:
   This bit does only exist in the 'dpm_win1_map'-register but not in the registers for the higher windows.
   However this bit protect all DPM 'dpm_winX_and' and 'dpm_winX_map'-registers from being written via
   configuration window 0.
Note:
   The 'wp_cfg_win'-bit is a new feature since netX4000 and netX6.
4 0
-
 reserved
3 - 2 "00"
win_map_alt
Window 1 Alternative Address Mapping Configuration.
Alternative Address Mapping can be generated by Triple Buffer Managers inside HANDSHAKE_CTRL unit.
Coding:
 00 : Alternative Address Mapping disabled.
 01 : Alternative Address Mapping enabled: Use Triple Buffer Manager 0 from HANDSHAKE_CTRL unit.
 10 : Alternative Address Mapping enabled: Use Triple Buffer Manager 1 from HANDSHAKE_CTRL unit.
 11 : reserved
If Alternative Address Mapping is enabled, mapping value is taken according to buffer status
of related HANDSHAKE_CTRL Triple Buffer Manager as follows.
 buffer status  used mapping value
 00 (buffer 0)  win_map entry of this register
 01 (buffer 1)  Alternative win_map value 1 of related HANDSHAKE_CTRL Triple Buffer Manager.
 10 (buffer 2)  Alternative win_map value 2 of related HANDSHAKE_CTRL Triple Buffer Manager.
 11 (invalid buffer)  win_map entry of this register
Note:
   Alternative Triple Buffer Manager win_map values can be programmed in HANDSHAKE_CTRL address area.
Note:
   For netX4000 there are 2 IDPM and 2 HANDSHAKE_CTRL units. IDPM0 is always associated with HANDSHAKE_CTRL0
   while IDPM1 is always associated with HANDSHAKE_CTRL1.
1 - 0 0
-
 reserved


idpm_win2_end
DPM Window 2 End Address Configuration Register.
For detailed information refer to 'idpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
0x00000000
Address : 0xff001b48
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 7 0x0
win_end
Window 2 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
-
 reserved


idpm_win2_map
DPM Window 2 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
0x00000000
Address : 0xff001b4c
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 - 7 "00000000"
win_map
Window address mapping.
6 - 4 0
-
 reserved
3 - 2 "00"
win_map_alt
Window Alternative Address Mapping Configuration.
1 - 0 0
-
 reserved


idpm_win3_end
DPM Window 3 End Address Configuration Register.
For detailed information refer to 'idpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
0x00000000
Address : 0xff001b50
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 7 0x0
win_end
Window 3 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
-
 reserved


idpm_win3_map
DPM Window 3 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
0x00000000
Address : 0xff001b54
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 - 7 "00000000"
win_map
Window map address.
6 - 4 0
-
 reserved
3 - 2 "00"
win_map_alt
Window Alternative Address Mapping Configuration.
1 - 0 0
-
 reserved


idpm_win4_end
DPM Window 4 End Address Configuration Register.
For detailed information refer to 'idpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
0x00000000
Address : 0xff001b58
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 7 0x0
win_end
Window 4 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
-
 reserved


idpm_win4_map
DPM Window 4 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'idpm_win1_map' register.
R/W
0x00000000
Address : 0xff001b5c
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 - 7 "00000000"
win_map
Window map address.
6 - 4 0
-
 reserved
3 - 2 "00"
win_map_alt
Window Alternative Address Mapping Configuration.
1 - 0 0
-
 reserved


idpm_irq_raw
DPM Raw (before masking) IRQ Status Register.
If a bit is set, the related interrupt is asserted.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.

Important: There are two completely independent sets of IRQ registers:
   IRQ register-set 1: 'dpm_irq_raw' (and related registers e.g. 'dpm_irq_irq_*' registers).
   IRQ register-set 2: 'dpm_firmware_irq_* registers' (netx50 compatible register set: DPM_HOST_INT_EN0,2 DPM_HOST_INT_STA0,2).
   Programming (masking or clearing IRQs) of one register-set has no impact to the other register-set even if some IRQs
   can be found in both sets (e.g. com0).

Note:
   The 'dpm_sw' IRQ can be controlled by the 'dpm_sw_irq' register.
   for each IRQ target. The 'dpm_sw' will be set inside the 'dpm_irq_raw' register
   when the 'dpm_sw' is activated for at least one IRQ target. But each IRQ target
   obtains only the 'dpm_sw' IRQ state programmed for this target inside the 'dpm_sw_irq'
   register. For an example view description of 'dpm_sw_irq' register.

Note:
    The 'firmware' IRQ can be used to flag handshake and netX firmware system status events to the
    host. Firmware IRQ generation can be controlled by dpm_firmware_irq_mask register. Detailed
    firmware IRQ status can be read from dpm_firmware_irq_raw register.
R
Address : 0xff001b80
Bits Name Description
31 - 3 -
 reserved
2 firmware
raw combined handshake-cell and SYS_STA firmware interrupt
1 -
 reserved
0 dpm_sw
raw software IRQ for IRQ targets interrupt


idpm_irq_host_mask_set
DPM Interrupt Mask Register for IDPM host interrupt.
Write access with '1' sets related interrupt mask bits (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for IDPM host interrupt.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for IDPM host interrupt without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
0x00000000
Address : 0xff001b84
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
firmware
set combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt
1 0
-
 reserved
0 "0"
dpm_sw
set software IRQ for IRQ targets interrupt mask for IDPM host interrupt


idpm_irq_host_mask_reset
DPM Interrupt Mask Reset Register for IDPM host interrupt.
Write access with '1' resets related interrupt mask bits (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for IDPM host interrupt.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for IDPM host interrupt without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
0x00000000
Address : 0xff001b88
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
firmware
reset combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt
1 0
-
 reserved
0 "0"
dpm_sw
reset software IRQ for IRQ targets interrupt mask for IDPM host interrupt


idpm_irq_host_masked
DPM Masked Interrupt Status Register for IDPM host interrupt.
A bit is set, when the related mask bit is set in 'dpm_irq_host_mask'-register and the related interrupt is asserted.
IRQ for IDPM host interrupt is asserted if at least one bit is set here.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for IDPM host interrupt without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R
Address : 0xff001b8c
Bits Name Description
31 - 3 -
 reserved
2 firmware
masked combined handshake-cell and SYS_STA firmware interrupt state for IDPM host interrupt
1 -
 reserved
0 dpm_sw
masked software IRQ for IRQ targets interrupt state for IDPM host interrupt


idpm_sw_irq
DPM Register for Software Interrupt Generation to Host and netX Interrupt Targets.
Host and netX masters can generate an interrupt to netX interrupt targets (e.g. ARM-VIC)
by this register.
To propagate interrupt states from this register to the interrupt target the 'idpm_sw' IRQ must
be enabled inside the appropriate interrupt controller (e.g. the ARM-VIC).

Note:
   There is a set and a reset bit for the sw-IRQ to avoid read-modify-write sequences.
   When both (set and reset) bits are set at the same time, the interrupt will be set (set will win).
   The reset-bit is always 0 for read. The set-bit shows the current interrupt status when read.
Note:
   This register is a new netx51/52 feature..
R/W
0x00000000
Address : 0xff001bc0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
reset_host
Reset 'dpm_sw' IRQ for host (always 0 when read)
7 - 1 0
-
 reserved
0 "0"
set_host
Set 'dpm_sw' IRQ for host (current 'dpm_sw' status for host when read)


idpm_sys_sta
(DPM_HOST_SYS_STAT)
DPM System Status Information Register.
This register can be used for firmware status information.

Note:
   This register is NOT fully compatible to netx50 DPM_HOST_SYS_STAT register:
   Only the HOST_STATE-bits of DPM0 can be read from the 'netx_status'-register inside ASIC_CTRL address area.
   The HOST_STATE-bits of DPM1 and IDPM can not be read from the 'netx_status'-register inside
   ASIC_CTRL address area.
R/W
0x00000000
Address : 0xff001bd8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
NETX_STA_CODE_ro
Bit field for Hilscher firmware compatibility (read only).
Note: This bit field can be changed by 'netx_status'-register inside ASIC_CTRL address area.
7 - 4 "0000"
HOST_STATE
Bit field for Hilscher firmware.
Note: This bit field can NOT be read from 'netx_status'-register inside ASIC_CTRL address area.
3 - 2 "00"
NETX_STATE_ro
Bit field for Hilscher firmware compatibility.
Note: This bit field can be changed by 'netx_status'-register inside ASIC_CTRL address area.
1 "0"
RUN_ro
Output state of netX RUN LED IO.
Note: This bit field can be changed by 'rdy_run_cfg'-register inside ASIC_CTRL address area.
0 "0"
RDY_ro
Output state of netX RDY LED IO.
Note: This bit field can be changed by 'rdy_run_cfg'-register inside ASIC_CTRL address area.


idpm_reset_request
(DPM_HOST_RESET_REQ)
DPM Reset Request Register.

Note: This register is compatible to netx50 DPM_HOST_RESET_REQ register
R/W
0x00000000
Address : 0xff001bdc
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
reset_key
Reset key sequence register.
A netx hardware reset is generated if the following sequence is written to this register:
  1st access: write 0x00
  2nd access: write 0x01
  3rd access: write 0x03
  4th access: write 0x07
  5th access: write 0x0f
  6th access: write 0x1f
  7th access: write 0x3f
  8th access: write 0x7f
To issue a reset the sequence must not be interrupted by a write access to another register
of this DPM module register area. Writing 0x00 will always restart the sequence.
Reading this register will always provide the next write data. Hence it is also possible
performing 8 times a read-write sequence to this register (however this is not required,
simply writing the sequence will also succeed).
Writing any other value than the next expected by the DPM module, the internal reset FSM will
be cleared and the register will return 0x00 for the next read. The FSM will also be cleared
if the sequence is interrupted by a write access to any other register of this DPM register
area. The sequence must be restarted with the 1st access (writing 0x00) in this case.
Note:
   The DPM reset request is internally a level-signal, not only a pulse. Additionally the
   DPM reset request could be masked (disabled) by the global reset controller (netX4000).
   If the DPM reset request is disabled globally but issued by the DPM module there are two
   possibilities to get out of this:
   1.: Enable the DPM reset in the global reset controller. The NETX will be reset then
immediately (typically this must be done by the NETX-side CPU and cannot be done by a host).
   2.:
Write 0x00 (or any other value except 0xFF) to this register or perform a write
access to any other register of this DPM register area. This will clear the DPM
reset FSM and the reset request of this DPM module to the global reset controller.


idpm_firmware_irq_raw
(DPM_HOST_INT_STAT0)
1st netx50 compatible DPM Interrupt Status Register (related to 'dpm_firmware_irq_mask'-register).
Writing a '1' to an IRQ flag will clear the Interrupt. This is always done even if related bit inside
'dpm_firmware_irq_mask'-register is not set (this is compatible to netx50).

Important:
   There are two completely independent sets of IRQ registers:
   IRQ register-set 1: 'dpm_irq_raw' (and related registers e.g. 'dpm_irq_irq_*' registers).
   IRQ register-set 2: 'dpm_firmware_irq_* registers' (netx50 compatible register set: DPM_HOST_INT_EN0,2 DPM_HOST_INT_STA0,2).
   Programming (masking or clearing IRQs) of one register-set has no impact to the other register-set even if some IRQs
   can be found in both sets (e.g. com0).

Note:
   This register is compatible to netx50 DPM_HOST_INT_STAT0 register, however some unused
   IRQs have been removed.

Note:
   For netX4000 there are 2 IDPM and 2 HANDSHAKE_CTRL units. IDPM0 is always associated with HANDSHAKE_CTRL0
   while IDPM1 is always associated with HANDSHAKE_CTRL1.

Note:
   The 2nd firmware IRQ register set (dpm_firmware_irq_mask2, DPM_HOST_INT_EN2, dpm_firmware_irq_raw2, DPM_HOST_INT_STAT2)
   are obsolete since netx4000. Some functions moved to the main DPM IRQ register set (view dpm_irq_raw).
R/W
0x00000000
Address : 0xff001be0
Bits Reset value Name Description
31 "0"
INT_REQ
Interrupt Request for IRQs handled in this register.
0: No Interrupts to host requested by IRQ sources handled in this register.
1: IRQ sources handled in this register request a host IRQ.
Note: This bit is masked by INT_EN-bit in dpm_firmware_irq_mask register.
   For propagation of INT_REQ to host, ARM or xPIC, INT_EN-bit must be set and firmware IRQ
   must be activated in related dpm_irq_* register.
30 "0"
res_MEM_LCK_ro
reserved for Memory Lock IRQ flag (not available in this netX version).
29 "0"
res_WDG_NETX_ro
reserved for netX supervision Watchdog Timeout IRQ flag (not available in this netX version).
28 "0"
res_RDY_TIMEOUT_ro
reserved, DPM_RDY timeout error does not exist for IDPM.
27 0
-
 reserved
26 "0"
SYS_STA
System Status Change IRQ flag.
25 "0"
res_TMR_ro
reserved for Timer IRQ flag (not available in this netX version).
24 0
-
 reserved
23 - 16 "00000000"
IRQ_VECTOR
Interrupt Vector according to status flags generated by enabled IRQ sources.
Code  IRQ status
0x00  No IRQ.
----  -------
0x10  Handshake Cell 0 IRQ.
0x11  Handshake Cell 1 IRQ.
0x12  Handshake Cell 2 IRQ.
0x13  Handshake Cell 3 IRQ.
0x14  Handshake Cell 4 IRQ.
0x15  Handshake Cell 5 IRQ.
0x16  Handshake Cell 6 IRQ.
0x17  Handshake Cell 7 IRQ.
0x18  Handshake Cell 8 IRQ.
0x19  Handshake Cell 9 IRQ.
0x1a  Handshake Cell 10 IRQ.
0x1b  Handshake Cell 11 IRQ.
0x1c  Handshake Cell 12 IRQ.
0x1d  Handshake Cell 13 IRQ.
0x1e  Handshake Cell 14 IRQ.
0x1f  Handshake Cell 15 IRQ.
----  -------
0x70  SYS_STA IRQ
Other  values are reserved.
Note:
   The current IRQ state in VECTOR depends only on the single IRQ enable bits. It
   does not depend on global IRQ enable INT_EN. VECTOR shows always the highest priority enabled
   flagged IRQ even is INT_EN is '0'.
15 "0"
HS_EVENT15
Handshake Event 15 IRQ status flag.
14 "0"
HS_EVENT14
Handshake Event 14 IRQ status flag.
13 "0"
HS_EVENT13
Handshake Event 13 IRQ status flag.
12 "0"
HS_EVENT12
Handshake Event 12 IRQ status flag.
11 "0"
HS_EVENT11
Handshake Event 11 IRQ status flag.
10 "0"
HS_EVENT10
Handshake Event 10 IRQ status flag.
9 "0"
HS_EVENT9
Handshake Event 9  IRQ status flag.
8 "0"
HS_EVENT8
Handshake Event 8  IRQ status flag.
7 "0"
HS_EVENT7
Handshake Event 7  IRQ status flag.
6 "0"
HS_EVENT6
Handshake Event 6  IRQ status flag.
5 "0"
HS_EVENT5
Handshake Event 5  IRQ status flag.
4 "0"
HS_EVENT4
Handshake Event 4  IRQ status flag.
3 "0"
HS_EVENT3
Handshake Event 3  IRQ status flag.
2 "0"
HS_EVENT2
Handshake Event 2  IRQ status flag.
1 "0"
HS_EVENT1
Handshake Event 1  IRQ status flag.
0 "0"
HS_EVENT0
Handshake Event 0  IRQ status flag.


idpm_firmware_irq_mask
(DPM_HOST_INT_EN0)
DPM Handshake Interrupt Enable Register.
Only netx50 compatible 'dpm_firmware_irq' registers are related to settings of this register.

Note: This register is compatible to netx50 DPM_HOST_INT_EN0 register, however some unused
   IRQs have been removed.

Note: HS_EVENT-bits are not read-only. This is netX50 compliant.
   Recent netX50 Documentation marks HS_EVENT-bits as read-only. This is an dokumentation error.
   For netX50 compatibility, these bits can also be controlled from netX-side in HANDSHAKE_CTRL address area.

Note: The 2nd firmware IRQ register set (dpm_firmware_irq_mask2, DPM_HOST_INT_EN2, dpm_firmware_irq_raw2, DPM_HOST_INT_STAT2)
   are obsolete since netx4000. Some functions moved to the main DPM IRQ register set (view dpm_irq_raw).
R/W
0x00000000
Address : 0xff001bf0
Bits Reset value Name Description
31 "0"
INT_EN
Interrupt Enable for IRQs handled in this register.
Only if this bit is set, global firmware IRQ will be asserted to host CPU, ARM or xPIC
by dpm_irq_* registers.
0: No Interrupts to host, ARM or xPIC are generated by IRQ sources handled in this register.
1: Enabled IRQ sources handled in this register generate a host, ARM or xPIC IRQ if asserted.
Note: Enable bits for single IRQ events are not affected if this bit is set or reset.
30 "0"
res_MEM_LCK_ro
reserved for Memory Lock IRQ (not available in this netX version).
29 "0"
res_WDG_NETX_ro
reserved for netX supervision Watchdog Timeout IRQ (not available in this netX version).
28 "0"
res_RDY_TIMEOUT_ro
reserved, DPM_RDY timeout error does not exist for IDPM.
27 0
-
 reserved
26 "0"
SYS_STA
System Status Change IRQ Enable.
25 "0"
res_TMR_ro
reserved for Timer IRQ (not available in this netX version).
24 - 16 0
-
 reserved
15 "0"
HS_EVENT15
Handshake Event 15 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
14 "0"
HS_EVENT14
Handshake Event 14 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
13 "0"
HS_EVENT13
Handshake Event 13 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
12 "0"
HS_EVENT12
Handshake Event 12 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
11 "0"
HS_EVENT11
Handshake Event 11 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
10 "0"
HS_EVENT10
Handshake Event 10 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
9 "0"
HS_EVENT9
Handshake Event 9  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
8 "0"
HS_EVENT8
Handshake Event 8  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
7 "0"
HS_EVENT7
Handshake Event 7  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
6 "0"
HS_EVENT6
Handshake Event 6  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
5 "0"
HS_EVENT5
Handshake Event 5  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
4 "0"
HS_EVENT4
Handshake Event 4  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
3 "0"
HS_EVENT3
Handshake Event 3  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
2 "0"
HS_EVENT2
Handshake Event 2  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
1 "0"
HS_EVENT1
Handshake Event 1  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).
0 "0"
HS_EVENT0
Handshake Event 0  IRQ Enable (also netX-controllable by HANDSHAKE_CTRL, netX50 comp.).


idpm_netx_version
DPM netX Version Register.
This register is mirrored form asic_ctrl register area and can be set during netX booting phase by netX firmware.
This register is not valid if unlocked bit is not set in dpm_status register.
Together with dpm_netx_version register, full 32 bit version can be read by any host device, even if DPM interface is not initialized yet.
Bytes byte0 and byte2 can be always read here even if DPM is uninitialized (8 bit default from dpm_cfg0x0 after power on) and
host device has 8, 16 or 32 bit data width.
R
Address : 0xff001bfc
Bits Name Description
31 - 0 netx_version
netX version from version register.



Base Address Area: hash

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 W hash_din
1 4 R/W hash_cfg
2 8 R hash_stat
3 c R hash_debug_info
4 10 R/W hash_irq_raw
5 14 R hash_irq_masked
6 18 R/W hash_irq_msk_set
7 1c R/W hash_irq_msk_reset
8 20 R hash_dout0
9 24 R hash_dout1
a 28 R hash_dout2
b 2c R hash_dout3
c 30 R hash_dout4
d 34 R hash_dout5
e 38 R hash_dout6
f 3c R hash_dout7
10 40 R hash_dout8
11 44 R hash_dout9
12 48 R hash_dout10
13 4c R hash_dout11
14 50 R hash_dout12
15 54 R hash_dout13
16 58 R hash_dout14
17 5c R hash_dout15
18-1f 60-7c -  reserved

hash_din
Hash FIFO input:
Unlike all other registers, this address can be written with DWord(32 Bit), Word(16 Bit) or Byte acccss.
The FIFO controller will automatically collect data and start HASH-calculation,
if enough data (complete DWords) are collected.
W
0x00000000
Address : 0xff080000
Bits Reset value Name Description
31 - 0 0x0
val
data bits


hash_cfg
Hash config register:
R/W
0x00000020
Address : 0xff080004
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "1"
dma_burst_only
Generate DMAC burst signal only.
When set to '1' the DMAC logic will only generate burst requests to the DMAC. This is to overcome limitations of the current DMA controller implementation that only accepts burst requests for DMAC controlled memory to peripheral transfers.
4 "0"
dma_en
Enable DMAC control signals
3 "0"
reset
Reset of SHA engine:
After writing '1', this bit will automatically be reset.
1: reset internal registers, use this to start calculation of new hash
0: start calculation as soon as enough data in FIFO buffer
2 - 0 "000"
mode
Hash core mode
100: MD5
011: SHA2-512
010: SHA2-384
001: SHA2-256
000: SHA1-160
Note: When changing the mode, a reset must be performed to correctly initialize the SHA/MD5 core. This can be done by setting the 'reset' bit together with the new mode or in a second access after setting the mode.


hash_stat
Hash status register:
R
Address : 0xff080008
Bits Name Description
31 - 9 -
 reserved
8 - 0 fifo_fill
Fill level of FIFO in bytes (0..256)


hash_debug_info
Hash info register:
R
Address : 0xff08000c
Bits Name Description
31 - 7 -
 reserved
6 - 0 sha_round
7bit current state counter of the SHA core.


hash_irq_raw
Hash raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0xff080010
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit.
1 "0"
fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit.
Note: underrun is only a theoretical FIFO status, because the hardware logic of the hash core won't fetch data from the FIFO when it's empty.
0 "0"
hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid.
Note: This interrupt will be asserted when the hash FIFO is empty and the calculation of the last block from the FIFO has finished. The interrupt will be re-asserted after clearing as long as no new data has been fed into the FIFO or a software reset has been performed (hash_cfg-reset=1).
Note: This interrupt could have got asserted in situations where the FIFO runs empty, the hash core finished the operation and new data blocks will be fed into the FIFO afterwards. In this case the IRQ will have been asserted before the very last block has been processed. In such situations it is advised to either disable the interrupt (hash_irq_mask_reset) and enable it after putting the very last data into the FIFO (hash_irq_mask_set) or to clear the IRQ once after putting the very last data and ignore any previous IRQs.


hash_irq_masked
Hash masked IRQ:
Shows status of masked IRQs.
R
Address : 0xff080014
Bits Name Description
31 - 3 -
 reserved
2 fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_irq_msk_set
Hash IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to crypt_hash_irq_raw.
R/W
0x00000000
Address : 0xff080018
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 "0"
fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 "0"
hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_irq_msk_reset
Hash IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address : 0xff08001c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 "0"
fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 "0"
hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_dout0
Hash value0 register
R
Address : 0xff080020
Bits Name Description
31 - 0 val
data bits 31..0


hash_dout1
Hash value1 register
R
Address : 0xff080024
Bits Name Description
31 - 0 val
data bits 63..32


hash_dout2
Hash value2 register
R
Address : 0xff080028
Bits Name Description
31 - 0 val
data bits 95..64


hash_dout3
Hash value3 register
R
Address : 0xff08002c
Bits Name Description
31 - 0 val
data bits 127..96


hash_dout4
Hash value4 register
R
Address : 0xff080030
Bits Name Description
31 - 0 val
data bits 159..128


hash_dout5
Hash value5 register
R
Address : 0xff080034
Bits Name Description
31 - 0 val
data bits 191..160


hash_dout6
Hash value6 register
R
Address : 0xff080038
Bits Name Description
31 - 0 val
data bits 223..192


hash_dout7
Hash value7 register
R
Address : 0xff08003c
Bits Name Description
31 - 0 val
data bits 255..224


hash_dout8
Hash value8 register
R
Address : 0xff080040
Bits Name Description
31 - 0 val
data bits 287..256


hash_dout9
Hash value9 register
R
Address : 0xff080044
Bits Name Description
31 - 0 val
data bits 319..288


hash_dout10
Hash value10 register
R
Address : 0xff080048
Bits Name Description
31 - 0 val
data bits 351..320


hash_dout11
Hash value11 register
R
Address : 0xff08004c
Bits Name Description
31 - 0 val
data bits 383..352


hash_dout12
Hash value12 register
R
Address : 0xff080050
Bits Name Description
31 - 0 val
data bits 415..384


hash_dout13
Hash value13 register
R
Address : 0xff080054
Bits Name Description
31 - 0 val
data bits 447..416


hash_dout14
Hash value14 register
R
Address : 0xff080058
Bits Name Description
31 - 0 val
data bits 479..448


hash_dout15
Hash value15 register
R
Address : 0xff08005c
Bits Name Description
31 - 0 val
data bits 511..480



Base Address Area: aes

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W aes_cfg
1 4 R aes_stat
2 8 R/W aes_irq_raw
3 c R aes_irq_masked
4 10 R/W aes_irq_msk_set
5 14 R/W aes_irq_msk_reset
6 18 R/W aes_key0
7 1c R/W aes_key1
8 20 R/W aes_key2
9 24 R/W aes_key3
a 28 R/W aes_key4
b 2c R/W aes_key5
c 30 R/W aes_key6
d 34 R/W aes_key7
e 38 W aes_din
f 3c R aes_dout

aes_cfg
AES config register
R/W
0x00148200
Address : 0xff080080
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 "1"
out_fifo_dma_burst_only
Generate DMAC burst signal only (output FIFO).
When set to '1' the DMAC logic will only generate burst requests to the DMAC. This is not strictly needed for the DMAC implementation, but could
result in better system performance.
19 "0"
out_fifo_dma_en
Enable DMAC control signals for the output FIFO.
18 "1"
in_fifo_dma_burst_only
Generate DMAC burst signal only (input FIFO).
When set to '1' the DMAC logic will only generate burst requests to the DMAC. This is to overcome limitations of the current DMA controller implementation that only accepts burst requests for DMAC controlled memory to peripheral transfers.
17 "0"
in_fifo_dma_en
Enable DMAC control signals for the input FIFO
16 - 11 "010000"
out_fifo_wm
Output FIFO watermark level (0..63) used for out_fifo_wm interrupt
10 - 5 "010000"
in_fifo_wm
Input FIFO watermark level (0..63) used for in_fifo_wm interrupt
4 "0"
key_exp_start
Start AES key expansion
After writing '1', this bit will automatically be reset. Data input can be started when key expansion is ready (see crypt_aes_stat bit 'key_exp_ready').
3 - 2 "00"
key_len
AES key length
0: 128 bit
1: 192 bit
2: 256 bit
3: reserved
1 "0"
mode
AES core operation mode
0: Encrypt
1: Decrypt
0 "0"
enable
Enables the AES core operation.


aes_stat
AES status register
R
Address : 0xff080084
Bits Name Description
31 - 28 -
 reserved
27 out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
Note: overflow is only a theoretical FIFO status, because the hardware logic of the AES core won't put data into the FIFO when it's full.
26 out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
25 out_fifo_not_full
Output FIFO is not full
24 out_fifo_full
Output FIFO is full
23 out_fifo_not_empty
Output FIFO is not empty
22 out_fifo_empty
Output FIFO is empty
21 - 15 out_fifo_fill
Fill level of output FIFO in bytes (0..64)
14 in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
13 in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
Note: underrun is only a theoretical FIFO status, because the hardware logic of the AES core won't fetch data from the FIFO when it's empty.
12 in_fifo_not_full
Input FIFO is not full
11 in_fifo_full
Input FIFO is full
10 in_fifo_not_empty
Input FIFO is not empty
9 in_fifo_empty
Input FIFO is empty
8 - 2 in_fifo_fill
Fill level of input FIFO in bytes (0..64)
1 op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 key_exp_ready
Set when key expansion procedure is done


aes_irq_raw
AES raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0xff080088
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
Note: overflow is only a theoretical FIFO status, because the hardware logic of the AES core won't put data into the FIFO when it's full.
14 "0"
out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
13 "0"
out_fifo_not_full
Output FIFO is not full
12 "0"
out_fifo_full
Output FIFO is full
11 "0"
out_fifo_not_empty
Output FIFO is not empty
10 "0"
out_fifo_empty
Output FIFO is empty
9 "0"
out_fifo_wm
Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')
8 "0"
in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
7 "0"
in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
Note: underrun is only a theoretical FIFO status, because the hardware logic of the AES core won't fetch data from the FIFO when it's empty.
6 "0"
in_fifo_not_full
Input FIFO is not full
5 "0"
in_fifo_full
Input FIFO is full
4 "0"
in_fifo_not_empty
Input FIFO is not empty
3 "0"
in_fifo_empty
Input FIFO is empty
2 "0"
in_fifo_wm
Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')
1 "0"
op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 "0"
key_exp_ready
Set when key expansion procedure is done


aes_irq_masked
AES masked IRQ:
Shows status of masked IRQs.
R
Address : 0xff08008c
Bits Name Description
31 - 16 -
 reserved
15 out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
14 out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
13 out_fifo_not_full
Output FIFO is not full
12 out_fifo_full
Output FIFO is full
11 out_fifo_not_empty
Output FIFO is not empty
10 out_fifo_empty
Output FIFO is empty
9 out_fifo_wm
Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')
8 in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
7 in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
6 in_fifo_not_full
Input FIFO is not full
5 in_fifo_full
Input FIFO is full
4 in_fifo_not_empty
Input FIFO is not empty
3 in_fifo_empty
Input FIFO is empty
2 in_fifo_wm
Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')
1 op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 key_exp_ready
Set when key expansion procedure is done


aes_irq_msk_set
AES IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to crypt_aes_irq_raw.
R/W
0x00000000
Address : 0xff080090
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
14 "0"
out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
13 "0"
out_fifo_not_full
Output FIFO is not full
12 "0"
out_fifo_full
Output FIFO is full
11 "0"
out_fifo_not_empty
Output FIFO is not empty
10 "0"
out_fifo_empty
Output FIFO is empty
9 "0"
out_fifo_wm
Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')
8 "0"
in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
7 "0"
in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
6 "0"
in_fifo_not_full
Input FIFO is not full
5 "0"
in_fifo_full
Input FIFO is full
4 "0"
in_fifo_not_empty
Input FIFO is not empty
3 "0"
in_fifo_empty
Input FIFO is empty
2 "0"
in_fifo_wm
Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')
1 "0"
op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 "0"
key_exp_ready
Set when key expansion procedure is done


aes_irq_msk_reset
AES IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address : 0xff080094
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
out_fifo_overflow
Output FIFO was overflown, set aes_cfg-enable=0 to reset this bit
14 "0"
out_fifo_underrun
Output FIFO was underrun, set aes_cfg-enable=0 to reset this bit
13 "0"
out_fifo_not_full
Output FIFO is not full
12 "0"
out_fifo_full
Output FIFO is full
11 "0"
out_fifo_not_empty
Output FIFO is not empty
10 "0"
out_fifo_empty
Output FIFO is empty
9 "0"
out_fifo_wm
Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')
8 "0"
in_fifo_overflow
Input FIFO was overflown, set aes_cfg-enable=0 to reset this bit
7 "0"
in_fifo_underrun
Input FIFO was underrun, set aes_cfg-enable=0 to reset this bit
6 "0"
in_fifo_not_full
Input FIFO is not full
5 "0"
in_fifo_full
Input FIFO is full
4 "0"
in_fifo_not_empty
Input FIFO is not empty
3 "0"
in_fifo_empty
Input FIFO is empty
2 "0"
in_fifo_wm
Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')
1 "0"
op_ready
Set when AES operation ready, i.e. AES core not busy and input
FIFO is empty
0 "0"
key_exp_ready
Set when key expansion procedure is done


aes_key0
AES key register 0
R/W
0x00000000
Address : 0xff080098
Bits Reset value Name Description
31 - 0 0x0
val
key bits 31..0


aes_key1
AES key register 1
R/W
0x00000000
Address : 0xff08009c
Bits Reset value Name Description
31 - 0 0x0
val
key bits 63..32


aes_key2
AES key register 2
R/W
0x00000000
Address : 0xff0800a0
Bits Reset value Name Description
31 - 0 0x0
val
key bits 95..64


aes_key3
AES key register 3
R/W
0x00000000
Address : 0xff0800a4
Bits Reset value Name Description
31 - 0 0x0
val
key bits 127..96


aes_key4
AES key register 4
R/W
0x00000000
Address : 0xff0800a8
Bits Reset value Name Description
31 - 0 0x0
val
key bits 159..128


aes_key5
AES key register 5
R/W
0x00000000
Address : 0xff0800ac
Bits Reset value Name Description
31 - 0 0x0
val
key bits 191..160


aes_key6
AES key register 6
R/W
0x00000000
Address : 0xff0800b0
Bits Reset value Name Description
31 - 0 0x0
val
key bits 223..192


aes_key7
AES key register 7
R/W
0x00000000
Address : 0xff0800b4
Bits Reset value Name Description
31 - 0 0x0
val
key bits 255..224


aes_din
AES FIFO input
Unlike all other registers, this address can be written with DWord(32 Bit), Word(16 Bit) or Byte acccss.
The FIFO controller will automatically collect data and start AES-calculation,
if enough data (4 DWords) are collected.
W
0x00000000
Address : 0xff0800b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits


aes_dout
AES FIFO output
R
Address : 0xff0800bc
Bits Name Description
31 - 0 val
data bits



Base Address Area: random

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W random_init
1 4 R random_random

random_init
Random initialization value:
Write a value depending on Chip ID to this register to generate a random sequence different for each netX.
R/W
0x55555555
Address : 0xff0800c0
Bits Reset value Name Description
31 - 0 0x55555555
val
random init value


random_random
Random value:
This random value sequence is derived from many random events inside netX chip.
R
Address : 0xff0800c4
Bits Name Description
31 - 0 val
random value



Base Address Area: mtgy

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mtgy_cmd
1 4 R mtgy_stat
2 8 R/W mtgy_irq_raw
3 c R mtgy_irq_masked
4 10 R/W mtgy_irq_msk_set
5 14 R/W mtgy_irq_msk_reset
6-3ff 18-ffc -  reserved
400 1000 R/W mtgy_op_tc0
401 1004 R/W mtgy_op_tc1
402 1008 R/W mtgy_op_tc2
403 100c R/W mtgy_op_tc3
404 1010 R/W mtgy_op_tc4
405 1014 R/W mtgy_op_tc5
406 1018 R/W mtgy_op_tc6
407 101c R/W mtgy_op_tc7
408 1020 R/W mtgy_op_tc8
409 1024 R/W mtgy_op_tc9
40a 1028 R/W mtgy_op_tc10
40b 102c R/W mtgy_op_tc11
40c 1030 R/W mtgy_op_tc12
40d 1034 R/W mtgy_op_tc13
40e 1038 R/W mtgy_op_tc14
40f 103c R/W mtgy_op_tc15
410 1040 R/W mtgy_op_tc16
411 1044 R/W mtgy_op_tc17
412 1048 R/W mtgy_op_tc18
413 104c R/W mtgy_op_tc19
414 1050 R/W mtgy_op_tc20
415 1054 R/W mtgy_op_tc21
416 1058 R/W mtgy_op_tc22
417 105c R/W mtgy_op_tc23
418 1060 R/W mtgy_op_tc24
419 1064 R/W mtgy_op_tc25
41a 1068 R/W mtgy_op_tc26
41b 106c R/W mtgy_op_tc27
41c 1070 R/W mtgy_op_tc28
41d 1074 R/W mtgy_op_tc29
41e 1078 R/W mtgy_op_tc30
41f 107c R/W mtgy_op_tc31
420 1080 R/W mtgy_op_tc32
421 1084 R/W mtgy_op_tc33
422 1088 R/W mtgy_op_tc34
423 108c R/W mtgy_op_tc35
424 1090 R/W mtgy_op_tc36
425 1094 R/W mtgy_op_tc37
426 1098 R/W mtgy_op_tc38
427 109c R/W mtgy_op_tc39
428 10a0 R/W mtgy_op_tc40
429 10a4 R/W mtgy_op_tc41
42a 10a8 R/W mtgy_op_tc42
42b 10ac R/W mtgy_op_tc43
42c 10b0 R/W mtgy_op_tc44
42d 10b4 R/W mtgy_op_tc45
42e 10b8 R/W mtgy_op_tc46
42f 10bc R/W mtgy_op_tc47
430 10c0 R/W mtgy_op_tc48
431 10c4 R/W mtgy_op_tc49
432 10c8 R/W mtgy_op_tc50
433 10cc R/W mtgy_op_tc51
434 10d0 R/W mtgy_op_tc52
435 10d4 R/W mtgy_op_tc53
436 10d8 R/W mtgy_op_tc54
437 10dc R/W mtgy_op_tc55
438 10e0 R/W mtgy_op_tc56
439 10e4 R/W mtgy_op_tc57
43a 10e8 R/W mtgy_op_tc58
43b 10ec R/W mtgy_op_tc59
43c 10f0 R/W mtgy_op_tc60
43d 10f4 R/W mtgy_op_tc61
43e 10f8 R/W mtgy_op_tc62
43f 10fc R/W mtgy_op_tc63
440 1100 R/W mtgy_op_tc64
441 1104 R/W mtgy_op_tc65
442 1108 R/W mtgy_op_tc66
443 110c R/W mtgy_op_tc67
444 1110 R/W mtgy_op_tc68
445 1114 R/W mtgy_op_tc69
446 1118 R/W mtgy_op_tc70
447 111c R/W mtgy_op_tc71
448 1120 R/W mtgy_op_tc72
449 1124 R/W mtgy_op_tc73
44a 1128 R/W mtgy_op_tc74
44b 112c R/W mtgy_op_tc75
44c 1130 R/W mtgy_op_tc76
44d 1134 R/W mtgy_op_tc77
44e 1138 R/W mtgy_op_tc78
44f 113c R/W mtgy_op_tc79
450 1140 R/W mtgy_op_tc80
451 1144 R/W mtgy_op_tc81
452 1148 R/W mtgy_op_tc82
453 114c R/W mtgy_op_tc83
454 1150 R/W mtgy_op_tc84
455 1154 R/W mtgy_op_tc85
456 1158 R/W mtgy_op_tc86
457 115c R/W mtgy_op_tc87
458 1160 R/W mtgy_op_tc88
459 1164 R/W mtgy_op_tc89
45a 1168 R/W mtgy_op_tc90
45b 116c R/W mtgy_op_tc91
45c 1170 R/W mtgy_op_tc92
45d 1174 R/W mtgy_op_tc93
45e 1178 R/W mtgy_op_tc94
45f 117c R/W mtgy_op_tc95
460 1180 R/W mtgy_op_tc96
461 1184 R/W mtgy_op_tc97
462 1188 R/W mtgy_op_tc98
463 118c R/W mtgy_op_tc99
464 1190 R/W mtgy_op_tc100
465 1194 R/W mtgy_op_tc101
466 1198 R/W mtgy_op_tc102
467 119c R/W mtgy_op_tc103
468 11a0 R/W mtgy_op_tc104
469 11a4 R/W mtgy_op_tc105
46a 11a8 R/W mtgy_op_tc106
46b 11ac R/W mtgy_op_tc107
46c 11b0 R/W mtgy_op_tc108
46d 11b4 R/W mtgy_op_tc109
46e 11b8 R/W mtgy_op_tc110
46f 11bc R/W mtgy_op_tc111
470 11c0 R/W mtgy_op_tc112
471 11c4 R/W mtgy_op_tc113
472 11c8 R/W mtgy_op_tc114
473 11cc R/W mtgy_op_tc115
474 11d0 R/W mtgy_op_tc116
475 11d4 R/W mtgy_op_tc117
476 11d8 R/W mtgy_op_tc118
477 11dc R/W mtgy_op_tc119
478 11e0 R/W mtgy_op_tc120
479 11e4 R/W mtgy_op_tc121
47a 11e8 R/W mtgy_op_tc122
47b 11ec R/W mtgy_op_tc123
47c 11f0 R/W mtgy_op_tc124
47d 11f4 R/W mtgy_op_tc125
47e 11f8 R/W mtgy_op_tc126
47f 11fc R/W mtgy_op_tc127
480 1200 R/W mtgy_op_ts0
481 1204 R/W mtgy_op_ts1
482 1208 R/W mtgy_op_ts2
483 120c R/W mtgy_op_ts3
484 1210 R/W mtgy_op_ts4
485 1214 R/W mtgy_op_ts5
486 1218 R/W mtgy_op_ts6
487 121c R/W mtgy_op_ts7
488 1220 R/W mtgy_op_ts8
489 1224 R/W mtgy_op_ts9
48a 1228 R/W mtgy_op_ts10
48b 122c R/W mtgy_op_ts11
48c 1230 R/W mtgy_op_ts12
48d 1234 R/W mtgy_op_ts13
48e 1238 R/W mtgy_op_ts14
48f 123c R/W mtgy_op_ts15
490 1240 R/W mtgy_op_ts16
491 1244 R/W mtgy_op_ts17
492 1248 R/W mtgy_op_ts18
493 124c R/W mtgy_op_ts19
494 1250 R/W mtgy_op_ts20
495 1254 R/W mtgy_op_ts21
496 1258 R/W mtgy_op_ts22
497 125c R/W mtgy_op_ts23
498 1260 R/W mtgy_op_ts24
499 1264 R/W mtgy_op_ts25
49a 1268 R/W mtgy_op_ts26
49b 126c R/W mtgy_op_ts27
49c 1270 R/W mtgy_op_ts28
49d 1274 R/W mtgy_op_ts29
49e 1278 R/W mtgy_op_ts30
49f 127c R/W mtgy_op_ts31
4a0 1280 R/W mtgy_op_ts32
4a1 1284 R/W mtgy_op_ts33
4a2 1288 R/W mtgy_op_ts34
4a3 128c R/W mtgy_op_ts35
4a4 1290 R/W mtgy_op_ts36
4a5 1294 R/W mtgy_op_ts37
4a6 1298 R/W mtgy_op_ts38
4a7 129c R/W mtgy_op_ts39
4a8 12a0 R/W mtgy_op_ts40
4a9 12a4 R/W mtgy_op_ts41
4aa 12a8 R/W mtgy_op_ts42
4ab 12ac R/W mtgy_op_ts43
4ac 12b0 R/W mtgy_op_ts44
4ad 12b4 R/W mtgy_op_ts45
4ae 12b8 R/W mtgy_op_ts46
4af 12bc R/W mtgy_op_ts47
4b0 12c0 R/W mtgy_op_ts48
4b1 12c4 R/W mtgy_op_ts49
4b2 12c8 R/W mtgy_op_ts50
4b3 12cc R/W mtgy_op_ts51
4b4 12d0 R/W mtgy_op_ts52
4b5 12d4 R/W mtgy_op_ts53
4b6 12d8 R/W mtgy_op_ts54
4b7 12dc R/W mtgy_op_ts55
4b8 12e0 R/W mtgy_op_ts56
4b9 12e4 R/W mtgy_op_ts57
4ba 12e8 R/W mtgy_op_ts58
4bb 12ec R/W mtgy_op_ts59
4bc 12f0 R/W mtgy_op_ts60
4bd 12f4 R/W mtgy_op_ts61
4be 12f8 R/W mtgy_op_ts62
4bf 12fc R/W mtgy_op_ts63
4c0 1300 R/W mtgy_op_ts64
4c1 1304 R/W mtgy_op_ts65
4c2 1308 R/W mtgy_op_ts66
4c3 130c R/W mtgy_op_ts67
4c4 1310 R/W mtgy_op_ts68
4c5 1314 R/W mtgy_op_ts69
4c6 1318 R/W mtgy_op_ts70
4c7 131c R/W mtgy_op_ts71
4c8 1320 R/W mtgy_op_ts72
4c9 1324 R/W mtgy_op_ts73
4ca 1328 R/W mtgy_op_ts74
4cb 132c R/W mtgy_op_ts75
4cc 1330 R/W mtgy_op_ts76
4cd 1334 R/W mtgy_op_ts77
4ce 1338 R/W mtgy_op_ts78
4cf 133c R/W mtgy_op_ts79
4d0 1340 R/W mtgy_op_ts80
4d1 1344 R/W mtgy_op_ts81
4d2 1348 R/W mtgy_op_ts82
4d3 134c R/W mtgy_op_ts83
4d4 1350 R/W mtgy_op_ts84
4d5 1354 R/W mtgy_op_ts85
4d6 1358 R/W mtgy_op_ts86
4d7 135c R/W mtgy_op_ts87
4d8 1360 R/W mtgy_op_ts88
4d9 1364 R/W mtgy_op_ts89
4da 1368 R/W mtgy_op_ts90
4db 136c R/W mtgy_op_ts91
4dc 1370 R/W mtgy_op_ts92
4dd 1374 R/W mtgy_op_ts93
4de 1378 R/W mtgy_op_ts94
4df 137c R/W mtgy_op_ts95
4e0 1380 R/W mtgy_op_ts96
4e1 1384 R/W mtgy_op_ts97
4e2 1388 R/W mtgy_op_ts98
4e3 138c R/W mtgy_op_ts99
4e4 1390 R/W mtgy_op_ts100
4e5 1394 R/W mtgy_op_ts101
4e6 1398 R/W mtgy_op_ts102
4e7 139c R/W mtgy_op_ts103
4e8 13a0 R/W mtgy_op_ts104
4e9 13a4 R/W mtgy_op_ts105
4ea 13a8 R/W mtgy_op_ts106
4eb 13ac R/W mtgy_op_ts107
4ec 13b0 R/W mtgy_op_ts108
4ed 13b4 R/W mtgy_op_ts109
4ee 13b8 R/W mtgy_op_ts110
4ef 13bc R/W mtgy_op_ts111
4f0 13c0 R/W mtgy_op_ts112
4f1 13c4 R/W mtgy_op_ts113
4f2 13c8 R/W mtgy_op_ts114
4f3 13cc R/W mtgy_op_ts115
4f4 13d0 R/W mtgy_op_ts116
4f5 13d4 R/W mtgy_op_ts117
4f6 13d8 R/W mtgy_op_ts118
4f7 13dc R/W mtgy_op_ts119
4f8 13e0 R/W mtgy_op_ts120
4f9 13e4 R/W mtgy_op_ts121
4fa 13e8 R/W mtgy_op_ts122
4fb 13ec R/W mtgy_op_ts123
4fc 13f0 R/W mtgy_op_ts124
4fd 13f4 R/W mtgy_op_ts125
4fe 13f8 R/W mtgy_op_ts126
4ff 13fc R/W mtgy_op_ts127
500 1400 R/W mtgy_op_p0
501 1404 R/W mtgy_op_p1
502 1408 R/W mtgy_op_p2
503 140c R/W mtgy_op_p3
504 1410 R/W mtgy_op_p4
505 1414 R/W mtgy_op_p5
506 1418 R/W mtgy_op_p6
507 141c R/W mtgy_op_p7
508 1420 R/W mtgy_op_p8
509 1424 R/W mtgy_op_p9
50a 1428 R/W mtgy_op_p10
50b 142c R/W mtgy_op_p11
50c 1430 R/W mtgy_op_p12
50d 1434 R/W mtgy_op_p13
50e 1438 R/W mtgy_op_p14
50f 143c R/W mtgy_op_p15
510 1440 R/W mtgy_op_p16
511 1444 R/W mtgy_op_p17
512 1448 R/W mtgy_op_p18
513 144c R/W mtgy_op_p19
514 1450 R/W mtgy_op_p20
515 1454 R/W mtgy_op_p21
516 1458 R/W mtgy_op_p22
517 145c R/W mtgy_op_p23
518 1460 R/W mtgy_op_p24
519 1464 R/W mtgy_op_p25
51a 1468 R/W mtgy_op_p26
51b 146c R/W mtgy_op_p27
51c 1470 R/W mtgy_op_p28
51d 1474 R/W mtgy_op_p29
51e 1478 R/W mtgy_op_p30
51f 147c R/W mtgy_op_p31
520 1480 R/W mtgy_op_p32
521 1484 R/W mtgy_op_p33
522 1488 R/W mtgy_op_p34
523 148c R/W mtgy_op_p35
524 1490 R/W mtgy_op_p36
525 1494 R/W mtgy_op_p37
526 1498 R/W mtgy_op_p38
527 149c R/W mtgy_op_p39
528 14a0 R/W mtgy_op_p40
529 14a4 R/W mtgy_op_p41
52a 14a8 R/W mtgy_op_p42
52b 14ac R/W mtgy_op_p43
52c 14b0 R/W mtgy_op_p44
52d 14b4 R/W mtgy_op_p45
52e 14b8 R/W mtgy_op_p46
52f 14bc R/W mtgy_op_p47
530 14c0 R/W mtgy_op_p48
531 14c4 R/W mtgy_op_p49
532 14c8 R/W mtgy_op_p50
533 14cc R/W mtgy_op_p51
534 14d0 R/W mtgy_op_p52
535 14d4 R/W mtgy_op_p53
536 14d8 R/W mtgy_op_p54
537 14dc R/W mtgy_op_p55
538 14e0 R/W mtgy_op_p56
539 14e4 R/W mtgy_op_p57
53a 14e8 R/W mtgy_op_p58
53b 14ec R/W mtgy_op_p59
53c 14f0 R/W mtgy_op_p60
53d 14f4 R/W mtgy_op_p61
53e 14f8 R/W mtgy_op_p62
53f 14fc R/W mtgy_op_p63
540 1500 R/W mtgy_op_p64
541 1504 R/W mtgy_op_p65
542 1508 R/W mtgy_op_p66
543 150c R/W mtgy_op_p67
544 1510 R/W mtgy_op_p68
545 1514 R/W mtgy_op_p69
546 1518 R/W mtgy_op_p70
547 151c R/W mtgy_op_p71
548 1520 R/W mtgy_op_p72
549 1524 R/W mtgy_op_p73
54a 1528 R/W mtgy_op_p74
54b 152c R/W mtgy_op_p75
54c 1530 R/W mtgy_op_p76
54d 1534 R/W mtgy_op_p77
54e 1538 R/W mtgy_op_p78
54f 153c R/W mtgy_op_p79
550 1540 R/W mtgy_op_p80
551 1544 R/W mtgy_op_p81
552 1548 R/W mtgy_op_p82
553 154c R/W mtgy_op_p83
554 1550 R/W mtgy_op_p84
555 1554 R/W mtgy_op_p85
556 1558 R/W mtgy_op_p86
557 155c R/W mtgy_op_p87
558 1560 R/W mtgy_op_p88
559 1564 R/W mtgy_op_p89
55a 1568 R/W mtgy_op_p90
55b 156c R/W mtgy_op_p91
55c 1570 R/W mtgy_op_p92
55d 1574 R/W mtgy_op_p93
55e 1578 R/W mtgy_op_p94
55f 157c R/W mtgy_op_p95
560 1580 R/W mtgy_op_p96
561 1584 R/W mtgy_op_p97
562 1588 R/W mtgy_op_p98
563 158c R/W mtgy_op_p99
564 1590 R/W mtgy_op_p100
565 1594 R/W mtgy_op_p101
566 1598 R/W mtgy_op_p102
567 159c R/W mtgy_op_p103
568 15a0 R/W mtgy_op_p104
569 15a4 R/W mtgy_op_p105
56a 15a8 R/W mtgy_op_p106
56b 15ac R/W mtgy_op_p107
56c 15b0 R/W mtgy_op_p108
56d 15b4 R/W mtgy_op_p109
56e 15b8 R/W mtgy_op_p110
56f 15bc R/W mtgy_op_p111
570 15c0 R/W mtgy_op_p112
571 15c4 R/W mtgy_op_p113
572 15c8 R/W mtgy_op_p114
573 15cc R/W mtgy_op_p115
574 15d0 R/W mtgy_op_p116
575 15d4 R/W mtgy_op_p117
576 15d8 R/W mtgy_op_p118
577 15dc R/W mtgy_op_p119
578 15e0 R/W mtgy_op_p120
579 15e4 R/W mtgy_op_p121
57a 15e8 R/W mtgy_op_p122
57b 15ec R/W mtgy_op_p123
57c 15f0 R/W mtgy_op_p124
57d 15f4 R/W mtgy_op_p125
57e 15f8 R/W mtgy_op_p126
57f 15fc R/W mtgy_op_p127
580 1600 R/W mtgy_op_b0
581 1604 R/W mtgy_op_b1
582 1608 R/W mtgy_op_b2
583 160c R/W mtgy_op_b3
584 1610 R/W mtgy_op_b4
585 1614 R/W mtgy_op_b5
586 1618 R/W mtgy_op_b6
587 161c R/W mtgy_op_b7
588 1620 R/W mtgy_op_b8
589 1624 R/W mtgy_op_b9
58a 1628 R/W mtgy_op_b10
58b 162c R/W mtgy_op_b11
58c 1630 R/W mtgy_op_b12
58d 1634 R/W mtgy_op_b13
58e 1638 R/W mtgy_op_b14
58f 163c R/W mtgy_op_b15
590 1640 R/W mtgy_op_b16
591 1644 R/W mtgy_op_b17
592 1648 R/W mtgy_op_b18
593 164c R/W mtgy_op_b19
594 1650 R/W mtgy_op_b20
595 1654 R/W mtgy_op_b21
596 1658 R/W mtgy_op_b22
597 165c R/W mtgy_op_b23
598 1660 R/W mtgy_op_b24
599 1664 R/W mtgy_op_b25
59a 1668 R/W mtgy_op_b26
59b 166c R/W mtgy_op_b27
59c 1670 R/W mtgy_op_b28
59d 1674 R/W mtgy_op_b29
59e 1678 R/W mtgy_op_b30
59f 167c R/W mtgy_op_b31
5a0 1680 R/W mtgy_op_b32
5a1 1684 R/W mtgy_op_b33
5a2 1688 R/W mtgy_op_b34
5a3 168c R/W mtgy_op_b35
5a4 1690 R/W mtgy_op_b36
5a5 1694 R/W mtgy_op_b37
5a6 1698 R/W mtgy_op_b38
5a7 169c R/W mtgy_op_b39
5a8 16a0 R/W mtgy_op_b40
5a9 16a4 R/W mtgy_op_b41
5aa 16a8 R/W mtgy_op_b42
5ab 16ac R/W mtgy_op_b43
5ac 16b0 R/W mtgy_op_b44
5ad 16b4 R/W mtgy_op_b45
5ae 16b8 R/W mtgy_op_b46
5af 16bc R/W mtgy_op_b47
5b0 16c0 R/W mtgy_op_b48
5b1 16c4 R/W mtgy_op_b49
5b2 16c8 R/W mtgy_op_b50
5b3 16cc R/W mtgy_op_b51
5b4 16d0 R/W mtgy_op_b52
5b5 16d4 R/W mtgy_op_b53
5b6 16d8 R/W mtgy_op_b54
5b7 16dc R/W mtgy_op_b55
5b8 16e0 R/W mtgy_op_b56
5b9 16e4 R/W mtgy_op_b57
5ba 16e8 R/W mtgy_op_b58
5bb 16ec R/W mtgy_op_b59
5bc 16f0 R/W mtgy_op_b60
5bd 16f4 R/W mtgy_op_b61
5be 16f8 R/W mtgy_op_b62
5bf 16fc R/W mtgy_op_b63
5c0 1700 R/W mtgy_op_b64
5c1 1704 R/W mtgy_op_b65
5c2 1708 R/W mtgy_op_b66
5c3 170c R/W mtgy_op_b67
5c4 1710 R/W mtgy_op_b68
5c5 1714 R/W mtgy_op_b69
5c6 1718 R/W mtgy_op_b70
5c7 171c R/W mtgy_op_b71
5c8 1720 R/W mtgy_op_b72
5c9 1724 R/W mtgy_op_b73
5ca 1728 R/W mtgy_op_b74
5cb 172c R/W mtgy_op_b75
5cc 1730 R/W mtgy_op_b76
5cd 1734 R/W mtgy_op_b77
5ce 1738 R/W mtgy_op_b78
5cf 173c R/W mtgy_op_b79
5d0 1740 R/W mtgy_op_b80
5d1 1744 R/W mtgy_op_b81
5d2 1748 R/W mtgy_op_b82
5d3 174c R/W mtgy_op_b83
5d4 1750 R/W mtgy_op_b84
5d5 1754 R/W mtgy_op_b85
5d6 1758 R/W mtgy_op_b86
5d7 175c R/W mtgy_op_b87
5d8 1760 R/W mtgy_op_b88
5d9 1764 R/W mtgy_op_b89
5da 1768 R/W mtgy_op_b90
5db 176c R/W mtgy_op_b91
5dc 1770 R/W mtgy_op_b92
5dd 1774 R/W mtgy_op_b93
5de 1778 R/W mtgy_op_b94
5df 177c R/W mtgy_op_b95
5e0 1780 R/W mtgy_op_b96
5e1 1784 R/W mtgy_op_b97
5e2 1788 R/W mtgy_op_b98
5e3 178c R/W mtgy_op_b99
5e4 1790 R/W mtgy_op_b100
5e5 1794 R/W mtgy_op_b101
5e6 1798 R/W mtgy_op_b102
5e7 179c R/W mtgy_op_b103
5e8 17a0 R/W mtgy_op_b104
5e9 17a4 R/W mtgy_op_b105
5ea 17a8 R/W mtgy_op_b106
5eb 17ac R/W mtgy_op_b107
5ec 17b0 R/W mtgy_op_b108
5ed 17b4 R/W mtgy_op_b109
5ee 17b8 R/W mtgy_op_b110
5ef 17bc R/W mtgy_op_b111
5f0 17c0 R/W mtgy_op_b112
5f1 17c4 R/W mtgy_op_b113
5f2 17c8 R/W mtgy_op_b114
5f3 17cc R/W mtgy_op_b115
5f4 17d0 R/W mtgy_op_b116
5f5 17d4 R/W mtgy_op_b117
5f6 17d8 R/W mtgy_op_b118
5f7 17dc R/W mtgy_op_b119
5f8 17e0 R/W mtgy_op_b120
5f9 17e4 R/W mtgy_op_b121
5fa 17e8 R/W mtgy_op_b122
5fb 17ec R/W mtgy_op_b123
5fc 17f0 R/W mtgy_op_b124
5fd 17f4 R/W mtgy_op_b125
5fe 17f8 R/W mtgy_op_b126
5ff 17fc R/W mtgy_op_b127
600 1800 R/W mtgy_op_a0
601 1804 R/W mtgy_op_a1
602 1808 R/W mtgy_op_a2
603 180c R/W mtgy_op_a3
604 1810 R/W mtgy_op_a4
605 1814 R/W mtgy_op_a5
606 1818 R/W mtgy_op_a6
607 181c R/W mtgy_op_a7
608 1820 R/W mtgy_op_a8
609 1824 R/W mtgy_op_a9
60a 1828 R/W mtgy_op_a10
60b 182c R/W mtgy_op_a11
60c 1830 R/W mtgy_op_a12
60d 1834 R/W mtgy_op_a13
60e 1838 R/W mtgy_op_a14
60f 183c R/W mtgy_op_a15
610 1840 R/W mtgy_op_a16
611 1844 R/W mtgy_op_a17
612 1848 R/W mtgy_op_a18
613 184c R/W mtgy_op_a19
614 1850 R/W mtgy_op_a20
615 1854 R/W mtgy_op_a21
616 1858 R/W mtgy_op_a22
617 185c R/W mtgy_op_a23
618 1860 R/W mtgy_op_a24
619 1864 R/W mtgy_op_a25
61a 1868 R/W mtgy_op_a26
61b 186c R/W mtgy_op_a27
61c 1870 R/W mtgy_op_a28
61d 1874 R/W mtgy_op_a29
61e 1878 R/W mtgy_op_a30
61f 187c R/W mtgy_op_a31
620 1880 R/W mtgy_op_a32
621 1884 R/W mtgy_op_a33
622 1888 R/W mtgy_op_a34
623 188c R/W mtgy_op_a35
624 1890 R/W mtgy_op_a36
625 1894 R/W mtgy_op_a37
626 1898 R/W mtgy_op_a38
627 189c R/W mtgy_op_a39
628 18a0 R/W mtgy_op_a40
629 18a4 R/W mtgy_op_a41
62a 18a8 R/W mtgy_op_a42
62b 18ac R/W mtgy_op_a43
62c 18b0 R/W mtgy_op_a44
62d 18b4 R/W mtgy_op_a45
62e 18b8 R/W mtgy_op_a46
62f 18bc R/W mtgy_op_a47
630 18c0 R/W mtgy_op_a48
631 18c4 R/W mtgy_op_a49
632 18c8 R/W mtgy_op_a50
633 18cc R/W mtgy_op_a51
634 18d0 R/W mtgy_op_a52
635 18d4 R/W mtgy_op_a53
636 18d8 R/W mtgy_op_a54
637 18dc R/W mtgy_op_a55
638 18e0 R/W mtgy_op_a56
639 18e4 R/W mtgy_op_a57
63a 18e8 R/W mtgy_op_a58
63b 18ec R/W mtgy_op_a59
63c 18f0 R/W mtgy_op_a60
63d 18f4 R/W mtgy_op_a61
63e 18f8 R/W mtgy_op_a62
63f 18fc R/W mtgy_op_a63
640 1900 R/W mtgy_op_a64
641 1904 R/W mtgy_op_a65
642 1908 R/W mtgy_op_a66
643 190c R/W mtgy_op_a67
644 1910 R/W mtgy_op_a68
645 1914 R/W mtgy_op_a69
646 1918 R/W mtgy_op_a70
647 191c R/W mtgy_op_a71
648 1920 R/W mtgy_op_a72
649 1924 R/W mtgy_op_a73
64a 1928 R/W mtgy_op_a74
64b 192c R/W mtgy_op_a75
64c 1930 R/W mtgy_op_a76
64d 1934 R/W mtgy_op_a77
64e 1938 R/W mtgy_op_a78
64f 193c R/W mtgy_op_a79
650 1940 R/W mtgy_op_a80
651 1944 R/W mtgy_op_a81
652 1948 R/W mtgy_op_a82
653 194c R/W mtgy_op_a83
654 1950 R/W mtgy_op_a84
655 1954 R/W mtgy_op_a85
656 1958 R/W mtgy_op_a86
657 195c R/W mtgy_op_a87
658 1960 R/W mtgy_op_a88
659 1964 R/W mtgy_op_a89
65a 1968 R/W mtgy_op_a90
65b 196c R/W mtgy_op_a91
65c 1970 R/W mtgy_op_a92
65d 1974 R/W mtgy_op_a93
65e 1978 R/W mtgy_op_a94
65f 197c R/W mtgy_op_a95
660 1980 R/W mtgy_op_a96
661 1984 R/W mtgy_op_a97
662 1988 R/W mtgy_op_a98
663 198c R/W mtgy_op_a99
664 1990 R/W mtgy_op_a100
665 1994 R/W mtgy_op_a101
666 1998 R/W mtgy_op_a102
667 199c R/W mtgy_op_a103
668 19a0 R/W mtgy_op_a104
669 19a4 R/W mtgy_op_a105
66a 19a8 R/W mtgy_op_a106
66b 19ac R/W mtgy_op_a107
66c 19b0 R/W mtgy_op_a108
66d 19b4 R/W mtgy_op_a109
66e 19b8 R/W mtgy_op_a110
66f 19bc R/W mtgy_op_a111
670 19c0 R/W mtgy_op_a112
671 19c4 R/W mtgy_op_a113
672 19c8 R/W mtgy_op_a114
673 19cc R/W mtgy_op_a115
674 19d0 R/W mtgy_op_a116
675 19d4 R/W mtgy_op_a117
676 19d8 R/W mtgy_op_a118
677 19dc R/W mtgy_op_a119
678 19e0 R/W mtgy_op_a120
679 19e4 R/W mtgy_op_a121
67a 19e8 R/W mtgy_op_a122
67b 19ec R/W mtgy_op_a123
67c 19f0 R/W mtgy_op_a124
67d 19f4 R/W mtgy_op_a125
67e 19f8 R/W mtgy_op_a126
67f 19fc R/W mtgy_op_a127
680 1a00 R/W mtgy_op_e0
681 1a04 R/W mtgy_op_e1
682 1a08 R/W mtgy_op_e2
683 1a0c R/W mtgy_op_e3
684 1a10 R/W mtgy_op_e4
685 1a14 R/W mtgy_op_e5
686 1a18 R/W mtgy_op_e6
687 1a1c R/W mtgy_op_e7
688 1a20 R/W mtgy_op_e8
689 1a24 R/W mtgy_op_e9
68a 1a28 R/W mtgy_op_e10
68b 1a2c R/W mtgy_op_e11
68c 1a30 R/W mtgy_op_e12
68d 1a34 R/W mtgy_op_e13
68e 1a38 R/W mtgy_op_e14
68f 1a3c R/W mtgy_op_e15
690 1a40 R/W mtgy_op_e16
691 1a44 R/W mtgy_op_e17
692 1a48 R/W mtgy_op_e18
693 1a4c R/W mtgy_op_e19
694 1a50 R/W mtgy_op_e20
695 1a54 R/W mtgy_op_e21
696 1a58 R/W mtgy_op_e22
697 1a5c R/W mtgy_op_e23
698 1a60 R/W mtgy_op_e24
699 1a64 R/W mtgy_op_e25
69a 1a68 R/W mtgy_op_e26
69b 1a6c R/W mtgy_op_e27
69c 1a70 R/W mtgy_op_e28
69d 1a74 R/W mtgy_op_e29
69e 1a78 R/W mtgy_op_e30
69f 1a7c R/W mtgy_op_e31
6a0 1a80 R/W mtgy_op_e32
6a1 1a84 R/W mtgy_op_e33
6a2 1a88 R/W mtgy_op_e34
6a3 1a8c R/W mtgy_op_e35
6a4 1a90 R/W mtgy_op_e36
6a5 1a94 R/W mtgy_op_e37
6a6 1a98 R/W mtgy_op_e38
6a7 1a9c R/W mtgy_op_e39
6a8 1aa0 R/W mtgy_op_e40
6a9 1aa4 R/W mtgy_op_e41
6aa 1aa8 R/W mtgy_op_e42
6ab 1aac R/W mtgy_op_e43
6ac 1ab0 R/W mtgy_op_e44
6ad 1ab4 R/W mtgy_op_e45
6ae 1ab8 R/W mtgy_op_e46
6af 1abc R/W mtgy_op_e47
6b0 1ac0 R/W mtgy_op_e48
6b1 1ac4 R/W mtgy_op_e49
6b2 1ac8 R/W mtgy_op_e50
6b3 1acc R/W mtgy_op_e51
6b4 1ad0 R/W mtgy_op_e52
6b5 1ad4 R/W mtgy_op_e53
6b6 1ad8 R/W mtgy_op_e54
6b7 1adc R/W mtgy_op_e55
6b8 1ae0 R/W mtgy_op_e56
6b9 1ae4 R/W mtgy_op_e57
6ba 1ae8 R/W mtgy_op_e58
6bb 1aec R/W mtgy_op_e59
6bc 1af0 R/W mtgy_op_e60
6bd 1af4 R/W mtgy_op_e61
6be 1af8 R/W mtgy_op_e62
6bf 1afc R/W mtgy_op_e63
6c0 1b00 R/W mtgy_op_e64
6c1 1b04 R/W mtgy_op_e65
6c2 1b08 R/W mtgy_op_e66
6c3 1b0c R/W mtgy_op_e67
6c4 1b10 R/W mtgy_op_e68
6c5 1b14 R/W mtgy_op_e69
6c6 1b18 R/W mtgy_op_e70
6c7 1b1c R/W mtgy_op_e71
6c8 1b20 R/W mtgy_op_e72
6c9 1b24 R/W mtgy_op_e73
6ca 1b28 R/W mtgy_op_e74
6cb 1b2c R/W mtgy_op_e75
6cc 1b30 R/W mtgy_op_e76
6cd 1b34 R/W mtgy_op_e77
6ce 1b38 R/W mtgy_op_e78
6cf 1b3c R/W mtgy_op_e79
6d0 1b40 R/W mtgy_op_e80
6d1 1b44 R/W mtgy_op_e81
6d2 1b48 R/W mtgy_op_e82
6d3 1b4c R/W mtgy_op_e83
6d4 1b50 R/W mtgy_op_e84
6d5 1b54 R/W mtgy_op_e85
6d6 1b58 R/W mtgy_op_e86
6d7 1b5c R/W mtgy_op_e87
6d8 1b60 R/W mtgy_op_e88
6d9 1b64 R/W mtgy_op_e89
6da 1b68 R/W mtgy_op_e90
6db 1b6c R/W mtgy_op_e91
6dc 1b70 R/W mtgy_op_e92
6dd 1b74 R/W mtgy_op_e93
6de 1b78 R/W mtgy_op_e94
6df 1b7c R/W mtgy_op_e95
6e0 1b80 R/W mtgy_op_e96
6e1 1b84 R/W mtgy_op_e97
6e2 1b88 R/W mtgy_op_e98
6e3 1b8c R/W mtgy_op_e99
6e4 1b90 R/W mtgy_op_e100
6e5 1b94 R/W mtgy_op_e101
6e6 1b98 R/W mtgy_op_e102
6e7 1b9c R/W mtgy_op_e103
6e8 1ba0 R/W mtgy_op_e104
6e9 1ba4 R/W mtgy_op_e105
6ea 1ba8 R/W mtgy_op_e106
6eb 1bac R/W mtgy_op_e107
6ec 1bb0 R/W mtgy_op_e108
6ed 1bb4 R/W mtgy_op_e109
6ee 1bb8 R/W mtgy_op_e110
6ef 1bbc R/W mtgy_op_e111
6f0 1bc0 R/W mtgy_op_e112
6f1 1bc4 R/W mtgy_op_e113
6f2 1bc8 R/W mtgy_op_e114
6f3 1bcc R/W mtgy_op_e115
6f4 1bd0 R/W mtgy_op_e116
6f5 1bd4 R/W mtgy_op_e117
6f6 1bd8 R/W mtgy_op_e118
6f7 1bdc R/W mtgy_op_e119
6f8 1be0 R/W mtgy_op_e120
6f9 1be4 R/W mtgy_op_e121
6fa 1be8 R/W mtgy_op_e122
6fb 1bec R/W mtgy_op_e123
6fc 1bf0 R/W mtgy_op_e124
6fd 1bf4 R/W mtgy_op_e125
6fe 1bf8 R/W mtgy_op_e126
6ff 1bfc R/W mtgy_op_e127
700 1c00 R/W mtgy_op_x0
701 1c04 R/W mtgy_op_x1
702 1c08 R/W mtgy_op_x2
703 1c0c R/W mtgy_op_x3
704 1c10 R/W mtgy_op_x4
705 1c14 R/W mtgy_op_x5
706 1c18 R/W mtgy_op_x6
707 1c1c R/W mtgy_op_x7
708 1c20 R/W mtgy_op_x8
709 1c24 R/W mtgy_op_x9
70a 1c28 R/W mtgy_op_x10
70b 1c2c R/W mtgy_op_x11
70c 1c30 R/W mtgy_op_x12
70d 1c34 R/W mtgy_op_x13
70e 1c38 R/W mtgy_op_x14
70f 1c3c R/W mtgy_op_x15
710 1c40 R/W mtgy_op_x16
711 1c44 R/W mtgy_op_x17
712 1c48 R/W mtgy_op_x18
713 1c4c R/W mtgy_op_x19
714 1c50 R/W mtgy_op_x20
715 1c54 R/W mtgy_op_x21
716 1c58 R/W mtgy_op_x22
717 1c5c R/W mtgy_op_x23
718 1c60 R/W mtgy_op_x24
719 1c64 R/W mtgy_op_x25
71a 1c68 R/W mtgy_op_x26
71b 1c6c R/W mtgy_op_x27
71c 1c70 R/W mtgy_op_x28
71d 1c74 R/W mtgy_op_x29
71e 1c78 R/W mtgy_op_x30
71f 1c7c R/W mtgy_op_x31
720 1c80 R/W mtgy_op_x32
721 1c84 R/W mtgy_op_x33
722 1c88 R/W mtgy_op_x34
723 1c8c R/W mtgy_op_x35
724 1c90 R/W mtgy_op_x36
725 1c94 R/W mtgy_op_x37
726 1c98 R/W mtgy_op_x38
727 1c9c R/W mtgy_op_x39
728 1ca0 R/W mtgy_op_x40
729 1ca4 R/W mtgy_op_x41
72a 1ca8 R/W mtgy_op_x42
72b 1cac R/W mtgy_op_x43
72c 1cb0 R/W mtgy_op_x44
72d 1cb4 R/W mtgy_op_x45
72e 1cb8 R/W mtgy_op_x46
72f 1cbc R/W mtgy_op_x47
730 1cc0 R/W mtgy_op_x48
731 1cc4 R/W mtgy_op_x49
732 1cc8 R/W mtgy_op_x50
733 1ccc R/W mtgy_op_x51
734 1cd0 R/W mtgy_op_x52
735 1cd4 R/W mtgy_op_x53
736 1cd8 R/W mtgy_op_x54
737 1cdc R/W mtgy_op_x55
738 1ce0 R/W mtgy_op_x56
739 1ce4 R/W mtgy_op_x57
73a 1ce8 R/W mtgy_op_x58
73b 1cec R/W mtgy_op_x59
73c 1cf0 R/W mtgy_op_x60
73d 1cf4 R/W mtgy_op_x61
73e 1cf8 R/W mtgy_op_x62
73f 1cfc R/W mtgy_op_x63
740 1d00 R/W mtgy_op_x64
741 1d04 R/W mtgy_op_x65
742 1d08 R/W mtgy_op_x66
743 1d0c R/W mtgy_op_x67
744 1d10 R/W mtgy_op_x68
745 1d14 R/W mtgy_op_x69
746 1d18 R/W mtgy_op_x70
747 1d1c R/W mtgy_op_x71
748 1d20 R/W mtgy_op_x72
749 1d24 R/W mtgy_op_x73
74a 1d28 R/W mtgy_op_x74
74b 1d2c R/W mtgy_op_x75
74c 1d30 R/W mtgy_op_x76
74d 1d34 R/W mtgy_op_x77
74e 1d38 R/W mtgy_op_x78
74f 1d3c R/W mtgy_op_x79
750 1d40 R/W mtgy_op_x80
751 1d44 R/W mtgy_op_x81
752 1d48 R/W mtgy_op_x82
753 1d4c R/W mtgy_op_x83
754 1d50 R/W mtgy_op_x84
755 1d54 R/W mtgy_op_x85
756 1d58 R/W mtgy_op_x86
757 1d5c R/W mtgy_op_x87
758 1d60 R/W mtgy_op_x88
759 1d64 R/W mtgy_op_x89
75a 1d68 R/W mtgy_op_x90
75b 1d6c R/W mtgy_op_x91
75c 1d70 R/W mtgy_op_x92
75d 1d74 R/W mtgy_op_x93
75e 1d78 R/W mtgy_op_x94
75f 1d7c R/W mtgy_op_x95
760 1d80 R/W mtgy_op_x96
761 1d84 R/W mtgy_op_x97
762 1d88 R/W mtgy_op_x98
763 1d8c R/W mtgy_op_x99
764 1d90 R/W mtgy_op_x100
765 1d94 R/W mtgy_op_x101
766 1d98 R/W mtgy_op_x102
767 1d9c R/W mtgy_op_x103
768 1da0 R/W mtgy_op_x104
769 1da4 R/W mtgy_op_x105
76a 1da8 R/W mtgy_op_x106
76b 1dac R/W mtgy_op_x107
76c 1db0 R/W mtgy_op_x108
76d 1db4 R/W mtgy_op_x109
76e 1db8 R/W mtgy_op_x110
76f 1dbc R/W mtgy_op_x111
770 1dc0 R/W mtgy_op_x112
771 1dc4 R/W mtgy_op_x113
772 1dc8 R/W mtgy_op_x114
773 1dcc R/W mtgy_op_x115
774 1dd0 R/W mtgy_op_x116
775 1dd4 R/W mtgy_op_x117
776 1dd8 R/W mtgy_op_x118
777 1ddc R/W mtgy_op_x119
778 1de0 R/W mtgy_op_x120
779 1de4 R/W mtgy_op_x121
77a 1de8 R/W mtgy_op_x122
77b 1dec R/W mtgy_op_x123
77c 1df0 R/W mtgy_op_x124
77d 1df4 R/W mtgy_op_x125
77e 1df8 R/W mtgy_op_x126
77f 1dfc R/W mtgy_op_x127
780-7ff 1e00-1ffc -  reserved

mtgy_cmd
MWMM command register:
R/W
0x00000094
Address : 0xff082000
Bits Reset value Name Description
31 - 27 "00000"
src_addr_x
Source address X specification.
The source address X specification will be interpreted as vertical RAM location source address offset of auxiliary operand E.
26 - 22 "00000"
src_addr_e
Source Address E specification.
The source address E specification will be interpreted as vertical RAM location source address offset of exponent E.
21 - 17 "00000"
dest_addr
Destination Address / Source Address A specification.
Depending on the operation the destination address specification will be interpreted as horizontal or vertical RAM location offset or as vertical RAM location source address offset of operand A.
16 - 12 "00000"
src_addr
Source Address specification.
Depending on the operation the source address specification will be interpreted as horizontal or vertical RAM location offset.
11 - 8 "0000"
op
The operation code of the core.
Following operations codes are supported:
0: MontMult (Montgomery Multiplication Step)
1: MontR (Montgomery Parameter R)
2: MontR2 (Montgomery Parameter R2 )
3: MontExp (Montgomery Exponentiation Step)
4: ModAdd (Modular Addition)
5: ModSub (Modular Subtraction)
6: CopyH2V (Copy from horizontal to vertical RAM location)
7: CopyV2V (Copy from vertical to vertical RAM location)
8: CopyH2H (Copy from horizontal to horizontal RAM location)
9: CopyV2H (Copy from vertical to horizontal RAM location)
10: MontMult1 (Montgomery Multiplication Step with '1' as A Operand)
7 - 4 "1001"
precision
Precision of executed operations.
0: 192 bit
1: 224 bit
2: 256 bit
3: 320 bit
4: 384 bit
5: 512 bit
6: 768 bit
7: 1024 bit
8: 1536 bit
9: 2048 bit
10: 3072 bit
11: 4096 bit
15 - 12: reserved
3 0
-
 reserved
2 "1"
f_sel
Finite Field Selection signal.
Defines if the calculations will be performed in
1: GF(p) or
0: GF(2^m).
1 "0"
abort
Abort Signal of the MWMM Core.
A running calculation can be aborted by issuing this signal.
After writing '1', this bit will automatically be reset.
0 "0"
start
Start Signal of the MWMM Core.
Setting this signal will instruct the Core to start the operation given by 'op' with precision specified by 'precision'. Depending on the operation the core will use the RAM location specified by 'src_addr', 'dest_addr', 'src_addr_e' and 'src_addr_x'. Calculations will be performed in the underlying finite field specified by 'f_sel'.
After writing '1', this bit will automatically be reset.


mtgy_stat
MWMM status register:
R
Address : 0xff082004
Bits Name Description
31 - 1 -
 reserved
0 done
Done signal from the MWMM core.


mtgy_irq_raw
MWMM raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0xff082008
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
done
Done signal from the MWMM core. Only a posedge on this signal will set the interrupt.


mtgy_irq_masked
MWMM masked IRQ:
Shows status of masked IRQs.
R
Address : 0xff08200c
Bits Name Description
31 - 1 -
 reserved
0 done
Done signal from the MWMM core.


mtgy_irq_msk_set
MWMM IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to mtgy_irq_raw.
R/W
0x00000000
Address : 0xff082010
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
done
Done signal from the MWMM core.


mtgy_irq_msk_reset
MWMM IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address : 0xff082014
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
done
Done signal from the MWMM core.


mtgy_op_tc0
MWMM TC register 0
R/W
0x00000000
Address : 0xff083000
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_tc1
MWMM TC register 1
R/W
0x00000000
Address : 0xff083004
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_tc2
MWMM TC register 2
R/W
0x00000000
Address : 0xff083008
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_tc3
MWMM TC register 3
R/W
0x00000000
Address : 0xff08300c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_tc4
MWMM TC register 4
R/W
0x00000000
Address : 0xff083010
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_tc5
MWMM TC register 5
R/W
0x00000000
Address : 0xff083014
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_tc6
MWMM TC register 6
R/W
0x00000000
Address : 0xff083018
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_tc7
MWMM TC register 7
R/W
0x00000000
Address : 0xff08301c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_tc8
MWMM TC register 8
R/W
0x00000000
Address : 0xff083020
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_tc9
MWMM TC register 9
R/W
0x00000000
Address : 0xff083024
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_tc10
MWMM TC register 10
R/W
0x00000000
Address : 0xff083028
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_tc11
MWMM TC register 11
R/W
0x00000000
Address : 0xff08302c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_tc12
MWMM TC register 12
R/W
0x00000000
Address : 0xff083030
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_tc13
MWMM TC register 13
R/W
0x00000000
Address : 0xff083034
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_tc14
MWMM TC register 14
R/W
0x00000000
Address : 0xff083038
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_tc15
MWMM TC register 15
R/W
0x00000000
Address : 0xff08303c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_tc16
MWMM TC register 16
R/W
0x00000000
Address : 0xff083040
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_tc17
MWMM TC register 17
R/W
0x00000000
Address : 0xff083044
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_tc18
MWMM TC register 18
R/W
0x00000000
Address : 0xff083048
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_tc19
MWMM TC register 19
R/W
0x00000000
Address : 0xff08304c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_tc20
MWMM TC register 20
R/W
0x00000000
Address : 0xff083050
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_tc21
MWMM TC register 21
R/W
0x00000000
Address : 0xff083054
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_tc22
MWMM TC register 22
R/W
0x00000000
Address : 0xff083058
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_tc23
MWMM TC register 23
R/W
0x00000000
Address : 0xff08305c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_tc24
MWMM TC register 24
R/W
0x00000000
Address : 0xff083060
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_tc25
MWMM TC register 25
R/W
0x00000000
Address : 0xff083064
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_tc26
MWMM TC register 26
R/W
0x00000000
Address : 0xff083068
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_tc27
MWMM TC register 27
R/W
0x00000000
Address : 0xff08306c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_tc28
MWMM TC register 28
R/W
0x00000000
Address : 0xff083070
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_tc29
MWMM TC register 29
R/W
0x00000000
Address : 0xff083074
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_tc30
MWMM TC register 30
R/W
0x00000000
Address : 0xff083078
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_tc31
MWMM TC register 31
R/W
0x00000000
Address : 0xff08307c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_tc32
MWMM TC register 32
R/W
0x00000000
Address : 0xff083080
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_tc33
MWMM TC register 33
R/W
0x00000000
Address : 0xff083084
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_tc34
MWMM TC register 34
R/W
0x00000000
Address : 0xff083088
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_tc35
MWMM TC register 35
R/W
0x00000000
Address : 0xff08308c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_tc36
MWMM TC register 36
R/W
0x00000000
Address : 0xff083090
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_tc37
MWMM TC register 37
R/W
0x00000000
Address : 0xff083094
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_tc38
MWMM TC register 38
R/W
0x00000000
Address : 0xff083098
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_tc39
MWMM TC register 39
R/W
0x00000000
Address : 0xff08309c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_tc40
MWMM TC register 40
R/W
0x00000000
Address : 0xff0830a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_tc41
MWMM TC register 41
R/W
0x00000000
Address : 0xff0830a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_tc42
MWMM TC register 42
R/W
0x00000000
Address : 0xff0830a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_tc43
MWMM TC register 43
R/W
0x00000000
Address : 0xff0830ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_tc44
MWMM TC register 44
R/W
0x00000000
Address : 0xff0830b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_tc45
MWMM TC register 45
R/W
0x00000000
Address : 0xff0830b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_tc46
MWMM TC register 46
R/W
0x00000000
Address : 0xff0830b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_tc47
MWMM TC register 47
R/W
0x00000000
Address : 0xff0830bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_tc48
MWMM TC register 48
R/W
0x00000000
Address : 0xff0830c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_tc49
MWMM TC register 49
R/W
0x00000000
Address : 0xff0830c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_tc50
MWMM TC register 50
R/W
0x00000000
Address : 0xff0830c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_tc51
MWMM TC register 51
R/W
0x00000000
Address : 0xff0830cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_tc52
MWMM TC register 52
R/W
0x00000000
Address : 0xff0830d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_tc53
MWMM TC register 53
R/W
0x00000000
Address : 0xff0830d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_tc54
MWMM TC register 54
R/W
0x00000000
Address : 0xff0830d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_tc55
MWMM TC register 55
R/W
0x00000000
Address : 0xff0830dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_tc56
MWMM TC register 56
R/W
0x00000000
Address : 0xff0830e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_tc57
MWMM TC register 57
R/W
0x00000000
Address : 0xff0830e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_tc58
MWMM TC register 58
R/W
0x00000000
Address : 0xff0830e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_tc59
MWMM TC register 59
R/W
0x00000000
Address : 0xff0830ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_tc60
MWMM TC register 60
R/W
0x00000000
Address : 0xff0830f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_tc61
MWMM TC register 61
R/W
0x00000000
Address : 0xff0830f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_tc62
MWMM TC register 62
R/W
0x00000000
Address : 0xff0830f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_tc63
MWMM TC register 63
R/W
0x00000000
Address : 0xff0830fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_tc64
MWMM TC register 64
R/W
0x00000000
Address : 0xff083100
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_tc65
MWMM TC register 65
R/W
0x00000000
Address : 0xff083104
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_tc66
MWMM TC register 66
R/W
0x00000000
Address : 0xff083108
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_tc67
MWMM TC register 67
R/W
0x00000000
Address : 0xff08310c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_tc68
MWMM TC register 68
R/W
0x00000000
Address : 0xff083110
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_tc69
MWMM TC register 69
R/W
0x00000000
Address : 0xff083114
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_tc70
MWMM TC register 70
R/W
0x00000000
Address : 0xff083118
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_tc71
MWMM TC register 71
R/W
0x00000000
Address : 0xff08311c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_tc72
MWMM TC register 72
R/W
0x00000000
Address : 0xff083120
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_tc73
MWMM TC register 73
R/W
0x00000000
Address : 0xff083124
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_tc74
MWMM TC register 74
R/W
0x00000000
Address : 0xff083128
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_tc75
MWMM TC register 75
R/W
0x00000000
Address : 0xff08312c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_tc76
MWMM TC register 76
R/W
0x00000000
Address : 0xff083130
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_tc77
MWMM TC register 77
R/W
0x00000000
Address : 0xff083134
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_tc78
MWMM TC register 78
R/W
0x00000000
Address : 0xff083138
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_tc79
MWMM TC register 79
R/W
0x00000000
Address : 0xff08313c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_tc80
MWMM TC register 80
R/W
0x00000000
Address : 0xff083140
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_tc81
MWMM TC register 81
R/W
0x00000000
Address : 0xff083144
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_tc82
MWMM TC register 82
R/W
0x00000000
Address : 0xff083148
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_tc83
MWMM TC register 83
R/W
0x00000000
Address : 0xff08314c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_tc84
MWMM TC register 84
R/W
0x00000000
Address : 0xff083150
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_tc85
MWMM TC register 85
R/W
0x00000000
Address : 0xff083154
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_tc86
MWMM TC register 86
R/W
0x00000000
Address : 0xff083158
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_tc87
MWMM TC register 87
R/W
0x00000000
Address : 0xff08315c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_tc88
MWMM TC register 88
R/W
0x00000000
Address : 0xff083160
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_tc89
MWMM TC register 89
R/W
0x00000000
Address : 0xff083164
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_tc90
MWMM TC register 90
R/W
0x00000000
Address : 0xff083168
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_tc91
MWMM TC register 91
R/W
0x00000000
Address : 0xff08316c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_tc92
MWMM TC register 92
R/W
0x00000000
Address : 0xff083170
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_tc93
MWMM TC register 93
R/W
0x00000000
Address : 0xff083174
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_tc94
MWMM TC register 94
R/W
0x00000000
Address : 0xff083178
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_tc95
MWMM TC register 95
R/W
0x00000000
Address : 0xff08317c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_tc96
MWMM TC register 96
R/W
0x00000000
Address : 0xff083180
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_tc97
MWMM TC register 97
R/W
0x00000000
Address : 0xff083184
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_tc98
MWMM TC register 98
R/W
0x00000000
Address : 0xff083188
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_tc99
MWMM TC register 99
R/W
0x00000000
Address : 0xff08318c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_tc100
MWMM TC register 100
R/W
0x00000000
Address : 0xff083190
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_tc101
MWMM TC register 101
R/W
0x00000000
Address : 0xff083194
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_tc102
MWMM TC register 102
R/W
0x00000000
Address : 0xff083198
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_tc103
MWMM TC register 103
R/W
0x00000000
Address : 0xff08319c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_tc104
MWMM TC register 104
R/W
0x00000000
Address : 0xff0831a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_tc105
MWMM TC register 105
R/W
0x00000000
Address : 0xff0831a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_tc106
MWMM TC register 106
R/W
0x00000000
Address : 0xff0831a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_tc107
MWMM TC register 107
R/W
0x00000000
Address : 0xff0831ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_tc108
MWMM TC register 108
R/W
0x00000000
Address : 0xff0831b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_tc109
MWMM TC register 109
R/W
0x00000000
Address : 0xff0831b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_tc110
MWMM TC register 110
R/W
0x00000000
Address : 0xff0831b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_tc111
MWMM TC register 111
R/W
0x00000000
Address : 0xff0831bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_tc112
MWMM TC register 112
R/W
0x00000000
Address : 0xff0831c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_tc113
MWMM TC register 113
R/W
0x00000000
Address : 0xff0831c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_tc114
MWMM TC register 114
R/W
0x00000000
Address : 0xff0831c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_tc115
MWMM TC register 115
R/W
0x00000000
Address : 0xff0831cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_tc116
MWMM TC register 116
R/W
0x00000000
Address : 0xff0831d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_tc117
MWMM TC register 117
R/W
0x00000000
Address : 0xff0831d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_tc118
MWMM TC register 118
R/W
0x00000000
Address : 0xff0831d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_tc119
MWMM TC register 119
R/W
0x00000000
Address : 0xff0831dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_tc120
MWMM TC register 120
R/W
0x00000000
Address : 0xff0831e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_tc121
MWMM TC register 121
R/W
0x00000000
Address : 0xff0831e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_tc122
MWMM TC register 122
R/W
0x00000000
Address : 0xff0831e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_tc123
MWMM TC register 123
R/W
0x00000000
Address : 0xff0831ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_tc124
MWMM TC register 124
R/W
0x00000000
Address : 0xff0831f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_tc125
MWMM TC register 125
R/W
0x00000000
Address : 0xff0831f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_tc126
MWMM TC register 126
R/W
0x00000000
Address : 0xff0831f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_tc127
MWMM TC register 127
R/W
0x00000000
Address : 0xff0831fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064


mtgy_op_ts0
MWMM TS register 0
R/W
0x00000000
Address : 0xff083200
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_ts1
MWMM TS register 1
R/W
0x00000000
Address : 0xff083204
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_ts2
MWMM TS register 2
R/W
0x00000000
Address : 0xff083208
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_ts3
MWMM TS register 3
R/W
0x00000000
Address : 0xff08320c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_ts4
MWMM TS register 4
R/W
0x00000000
Address : 0xff083210
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_ts5
MWMM TS register 5
R/W
0x00000000
Address : 0xff083214
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_ts6
MWMM TS register 6
R/W
0x00000000
Address : 0xff083218
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_ts7
MWMM TS register 7
R/W
0x00000000
Address : 0xff08321c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_ts8
MWMM TS register 8
R/W
0x00000000
Address : 0xff083220
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_ts9
MWMM TS register 9
R/W
0x00000000
Address : 0xff083224
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_ts10
MWMM TS register 10
R/W
0x00000000
Address : 0xff083228
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_ts11
MWMM TS register 11
R/W
0x00000000
Address : 0xff08322c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_ts12
MWMM TS register 12
R/W
0x00000000
Address : 0xff083230
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_ts13
MWMM TS register 13
R/W
0x00000000
Address : 0xff083234
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_ts14
MWMM TS register 14
R/W
0x00000000
Address : 0xff083238
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_ts15
MWMM TS register 15
R/W
0x00000000
Address : 0xff08323c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_ts16
MWMM TS register 16
R/W
0x00000000
Address : 0xff083240
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_ts17
MWMM TS register 17
R/W
0x00000000
Address : 0xff083244
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_ts18
MWMM TS register 18
R/W
0x00000000
Address : 0xff083248
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_ts19
MWMM TS register 19
R/W
0x00000000
Address : 0xff08324c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_ts20
MWMM TS register 20
R/W
0x00000000
Address : 0xff083250
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_ts21
MWMM TS register 21
R/W
0x00000000
Address : 0xff083254
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_ts22
MWMM TS register 22
R/W
0x00000000
Address : 0xff083258
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_ts23
MWMM TS register 23
R/W
0x00000000
Address : 0xff08325c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_ts24
MWMM TS register 24
R/W
0x00000000
Address : 0xff083260
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_ts25
MWMM TS register 25
R/W
0x00000000
Address : 0xff083264
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_ts26
MWMM TS register 26
R/W
0x00000000
Address : 0xff083268
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_ts27
MWMM TS register 27
R/W
0x00000000
Address : 0xff08326c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_ts28
MWMM TS register 28
R/W
0x00000000
Address : 0xff083270
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_ts29
MWMM TS register 29
R/W
0x00000000
Address : 0xff083274
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_ts30
MWMM TS register 30
R/W
0x00000000
Address : 0xff083278
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_ts31
MWMM TS register 31
R/W
0x00000000
Address : 0xff08327c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_ts32
MWMM TS register 32
R/W
0x00000000
Address : 0xff083280
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_ts33
MWMM TS register 33
R/W
0x00000000
Address : 0xff083284
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_ts34
MWMM TS register 34
R/W
0x00000000
Address : 0xff083288
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_ts35
MWMM TS register 35
R/W
0x00000000
Address : 0xff08328c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_ts36
MWMM TS register 36
R/W
0x00000000
Address : 0xff083290
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_ts37
MWMM TS register 37
R/W
0x00000000
Address : 0xff083294
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_ts38
MWMM TS register 38
R/W
0x00000000
Address : 0xff083298
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_ts39
MWMM TS register 39
R/W
0x00000000
Address : 0xff08329c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_ts40
MWMM TS register 40
R/W
0x00000000
Address : 0xff0832a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_ts41
MWMM TS register 41
R/W
0x00000000
Address : 0xff0832a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_ts42
MWMM TS register 42
R/W
0x00000000
Address : 0xff0832a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_ts43
MWMM TS register 43
R/W
0x00000000
Address : 0xff0832ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_ts44
MWMM TS register 44
R/W
0x00000000
Address : 0xff0832b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_ts45
MWMM TS register 45
R/W
0x00000000
Address : 0xff0832b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_ts46
MWMM TS register 46
R/W
0x00000000
Address : 0xff0832b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_ts47
MWMM TS register 47
R/W
0x00000000
Address : 0xff0832bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_ts48
MWMM TS register 48
R/W
0x00000000
Address : 0xff0832c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_ts49
MWMM TS register 49
R/W
0x00000000
Address : 0xff0832c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_ts50
MWMM TS register 50
R/W
0x00000000
Address : 0xff0832c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_ts51
MWMM TS register 51
R/W
0x00000000
Address : 0xff0832cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_ts52
MWMM TS register 52
R/W
0x00000000
Address : 0xff0832d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_ts53
MWMM TS register 53
R/W
0x00000000
Address : 0xff0832d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_ts54
MWMM TS register 54
R/W
0x00000000
Address : 0xff0832d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_ts55
MWMM TS register 55
R/W
0x00000000
Address : 0xff0832dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_ts56
MWMM TS register 56
R/W
0x00000000
Address : 0xff0832e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_ts57
MWMM TS register 57
R/W
0x00000000
Address : 0xff0832e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_ts58
MWMM TS register 58
R/W
0x00000000
Address : 0xff0832e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_ts59
MWMM TS register 59
R/W
0x00000000
Address : 0xff0832ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_ts60
MWMM TS register 60
R/W
0x00000000
Address : 0xff0832f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_ts61
MWMM TS register 61
R/W
0x00000000
Address : 0xff0832f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_ts62
MWMM TS register 62
R/W
0x00000000
Address : 0xff0832f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_ts63
MWMM TS register 63
R/W
0x00000000
Address : 0xff0832fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_ts64
MWMM TS register 64
R/W
0x00000000
Address : 0xff083300
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_ts65
MWMM TS register 65
R/W
0x00000000
Address : 0xff083304
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_ts66
MWMM TS register 66
R/W
0x00000000
Address : 0xff083308
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_ts67
MWMM TS register 67
R/W
0x00000000
Address : 0xff08330c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_ts68
MWMM TS register 68
R/W
0x00000000
Address : 0xff083310
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_ts69
MWMM TS register 69
R/W
0x00000000
Address : 0xff083314
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_ts70
MWMM TS register 70
R/W
0x00000000
Address : 0xff083318
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_ts71
MWMM TS register 71
R/W
0x00000000
Address : 0xff08331c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_ts72
MWMM TS register 72
R/W
0x00000000
Address : 0xff083320
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_ts73
MWMM TS register 73
R/W
0x00000000
Address : 0xff083324
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_ts74
MWMM TS register 74
R/W
0x00000000
Address : 0xff083328
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_ts75
MWMM TS register 75
R/W
0x00000000
Address : 0xff08332c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_ts76
MWMM TS register 76
R/W
0x00000000
Address : 0xff083330
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_ts77
MWMM TS register 77
R/W
0x00000000
Address : 0xff083334
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_ts78
MWMM TS register 78
R/W
0x00000000
Address : 0xff083338
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_ts79
MWMM TS register 79
R/W
0x00000000
Address : 0xff08333c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_ts80
MWMM TS register 80
R/W
0x00000000
Address : 0xff083340
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_ts81
MWMM TS register 81
R/W
0x00000000
Address : 0xff083344
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_ts82
MWMM TS register 82
R/W
0x00000000
Address : 0xff083348
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_ts83
MWMM TS register 83
R/W
0x00000000
Address : 0xff08334c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_ts84
MWMM TS register 84
R/W
0x00000000
Address : 0xff083350
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_ts85
MWMM TS register 85
R/W
0x00000000
Address : 0xff083354
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_ts86
MWMM TS register 86
R/W
0x00000000
Address : 0xff083358
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_ts87
MWMM TS register 87
R/W
0x00000000
Address : 0xff08335c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_ts88
MWMM TS register 88
R/W
0x00000000
Address : 0xff083360
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_ts89
MWMM TS register 89
R/W
0x00000000
Address : 0xff083364
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_ts90
MWMM TS register 90
R/W
0x00000000
Address : 0xff083368
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_ts91
MWMM TS register 91
R/W
0x00000000
Address : 0xff08336c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_ts92
MWMM TS register 92
R/W
0x00000000
Address : 0xff083370
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_ts93
MWMM TS register 93
R/W
0x00000000
Address : 0xff083374
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_ts94
MWMM TS register 94
R/W
0x00000000
Address : 0xff083378
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_ts95
MWMM TS register 95
R/W
0x00000000
Address : 0xff08337c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_ts96
MWMM TS register 96
R/W
0x00000000
Address : 0xff083380
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_ts97
MWMM TS register 97
R/W
0x00000000
Address : 0xff083384
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_ts98
MWMM TS register 98
R/W
0x00000000
Address : 0xff083388
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_ts99
MWMM TS register 99
R/W
0x00000000
Address : 0xff08338c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_ts100
MWMM TS register 100
R/W
0x00000000
Address : 0xff083390
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_ts101
MWMM TS register 101
R/W
0x00000000
Address : 0xff083394
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_ts102
MWMM TS register 102
R/W
0x00000000
Address : 0xff083398
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_ts103
MWMM TS register 103
R/W
0x00000000
Address : 0xff08339c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_ts104
MWMM TS register 104
R/W
0x00000000
Address : 0xff0833a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_ts105
MWMM TS register 105
R/W
0x00000000
Address : 0xff0833a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_ts106
MWMM TS register 106
R/W
0x00000000
Address : 0xff0833a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_ts107
MWMM TS register 107
R/W
0x00000000
Address : 0xff0833ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_ts108
MWMM TS register 108
R/W
0x00000000
Address : 0xff0833b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_ts109
MWMM TS register 109
R/W
0x00000000
Address : 0xff0833b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_ts110
MWMM TS register 110
R/W
0x00000000
Address : 0xff0833b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_ts111
MWMM TS register 111
R/W
0x00000000
Address : 0xff0833bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_ts112
MWMM TS register 112
R/W
0x00000000
Address : 0xff0833c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_ts113
MWMM TS register 113
R/W
0x00000000
Address : 0xff0833c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_ts114
MWMM TS register 114
R/W
0x00000000
Address : 0xff0833c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_ts115
MWMM TS register 115
R/W
0x00000000
Address : 0xff0833cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_ts116
MWMM TS register 116
R/W
0x00000000
Address : 0xff0833d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_ts117
MWMM TS register 117
R/W
0x00000000
Address : 0xff0833d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_ts118
MWMM TS register 118
R/W
0x00000000
Address : 0xff0833d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_ts119
MWMM TS register 119
R/W
0x00000000
Address : 0xff0833dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_ts120
MWMM TS register 120
R/W
0x00000000
Address : 0xff0833e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_ts121
MWMM TS register 121
R/W
0x00000000
Address : 0xff0833e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_ts122
MWMM TS register 122
R/W
0x00000000
Address : 0xff0833e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_ts123
MWMM TS register 123
R/W
0x00000000
Address : 0xff0833ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_ts124
MWMM TS register 124
R/W
0x00000000
Address : 0xff0833f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_ts125
MWMM TS register 125
R/W
0x00000000
Address : 0xff0833f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_ts126
MWMM TS register 126
R/W
0x00000000
Address : 0xff0833f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_ts127
MWMM TS register 127
R/W
0x00000000
Address : 0xff0833fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064


mtgy_op_p0
MWMM operand P register 0
R/W
0x00000000
Address : 0xff083400
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_p1
MWMM operand P register 1
R/W
0x00000000
Address : 0xff083404
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_p2
MWMM operand P register 2
R/W
0x00000000
Address : 0xff083408
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_p3
MWMM operand P register 3
R/W
0x00000000
Address : 0xff08340c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_p4
MWMM operand P register 4
R/W
0x00000000
Address : 0xff083410
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_p5
MWMM operand P register 5
R/W
0x00000000
Address : 0xff083414
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_p6
MWMM operand P register 6
R/W
0x00000000
Address : 0xff083418
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_p7
MWMM operand P register 7
R/W
0x00000000
Address : 0xff08341c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_p8
MWMM operand P register 8
R/W
0x00000000
Address : 0xff083420
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_p9
MWMM operand P register 9
R/W
0x00000000
Address : 0xff083424
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_p10
MWMM operand P register 10
R/W
0x00000000
Address : 0xff083428
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_p11
MWMM operand P register 11
R/W
0x00000000
Address : 0xff08342c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_p12
MWMM operand P register 12
R/W
0x00000000
Address : 0xff083430
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_p13
MWMM operand P register 13
R/W
0x00000000
Address : 0xff083434
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_p14
MWMM operand P register 14
R/W
0x00000000
Address : 0xff083438
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_p15
MWMM operand P register 15
R/W
0x00000000
Address : 0xff08343c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_p16
MWMM operand P register 16
R/W
0x00000000
Address : 0xff083440
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_p17
MWMM operand P register 17
R/W
0x00000000
Address : 0xff083444
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_p18
MWMM operand P register 18
R/W
0x00000000
Address : 0xff083448
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_p19
MWMM operand P register 19
R/W
0x00000000
Address : 0xff08344c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_p20
MWMM operand P register 20
R/W
0x00000000
Address : 0xff083450
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_p21
MWMM operand P register 21
R/W
0x00000000
Address : 0xff083454
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_p22
MWMM operand P register 22
R/W
0x00000000
Address : 0xff083458
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_p23
MWMM operand P register 23
R/W
0x00000000
Address : 0xff08345c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_p24
MWMM operand P register 24
R/W
0x00000000
Address : 0xff083460
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_p25
MWMM operand P register 25
R/W
0x00000000
Address : 0xff083464
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_p26
MWMM operand P register 26
R/W
0x00000000
Address : 0xff083468
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_p27
MWMM operand P register 27
R/W
0x00000000
Address : 0xff08346c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_p28
MWMM operand P register 28
R/W
0x00000000
Address : 0xff083470
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_p29
MWMM operand P register 29
R/W
0x00000000
Address : 0xff083474
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_p30
MWMM operand P register 30
R/W
0x00000000
Address : 0xff083478
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_p31
MWMM operand P register 31
R/W
0x00000000
Address : 0xff08347c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_p32
MWMM operand P register 32
R/W
0x00000000
Address : 0xff083480
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_p33
MWMM operand P register 33
R/W
0x00000000
Address : 0xff083484
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_p34
MWMM operand P register 34
R/W
0x00000000
Address : 0xff083488
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_p35
MWMM operand P register 35
R/W
0x00000000
Address : 0xff08348c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_p36
MWMM operand P register 36
R/W
0x00000000
Address : 0xff083490
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_p37
MWMM operand P register 37
R/W
0x00000000
Address : 0xff083494
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_p38
MWMM operand P register 38
R/W
0x00000000
Address : 0xff083498
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_p39
MWMM operand P register 39
R/W
0x00000000
Address : 0xff08349c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_p40
MWMM operand P register 40
R/W
0x00000000
Address : 0xff0834a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_p41
MWMM operand P register 41
R/W
0x00000000
Address : 0xff0834a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_p42
MWMM operand P register 42
R/W
0x00000000
Address : 0xff0834a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_p43
MWMM operand P register 43
R/W
0x00000000
Address : 0xff0834ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_p44
MWMM operand P register 44
R/W
0x00000000
Address : 0xff0834b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_p45
MWMM operand P register 45
R/W
0x00000000
Address : 0xff0834b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_p46
MWMM operand P register 46
R/W
0x00000000
Address : 0xff0834b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_p47
MWMM operand P register 47
R/W
0x00000000
Address : 0xff0834bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_p48
MWMM operand P register 48
R/W
0x00000000
Address : 0xff0834c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_p49
MWMM operand P register 49
R/W
0x00000000
Address : 0xff0834c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_p50
MWMM operand P register 50
R/W
0x00000000
Address : 0xff0834c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_p51
MWMM operand P register 51
R/W
0x00000000
Address : 0xff0834cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_p52
MWMM operand P register 52
R/W
0x00000000
Address : 0xff0834d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_p53
MWMM operand P register 53
R/W
0x00000000
Address : 0xff0834d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_p54
MWMM operand P register 54
R/W
0x00000000
Address : 0xff0834d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_p55
MWMM operand P register 55
R/W
0x00000000
Address : 0xff0834dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_p56
MWMM operand P register 56
R/W
0x00000000
Address : 0xff0834e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_p57
MWMM operand P register 57
R/W
0x00000000
Address : 0xff0834e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_p58
MWMM operand P register 58
R/W
0x00000000
Address : 0xff0834e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_p59
MWMM operand P register 59
R/W
0x00000000
Address : 0xff0834ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_p60
MWMM operand P register 60
R/W
0x00000000
Address : 0xff0834f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_p61
MWMM operand P register 61
R/W
0x00000000
Address : 0xff0834f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_p62
MWMM operand P register 62
R/W
0x00000000
Address : 0xff0834f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_p63
MWMM operand P register 63
R/W
0x00000000
Address : 0xff0834fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_p64
MWMM operand P register 64
R/W
0x00000000
Address : 0xff083500
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_p65
MWMM operand P register 65
R/W
0x00000000
Address : 0xff083504
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_p66
MWMM operand P register 66
R/W
0x00000000
Address : 0xff083508
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_p67
MWMM operand P register 67
R/W
0x00000000
Address : 0xff08350c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_p68
MWMM operand P register 68
R/W
0x00000000
Address : 0xff083510
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_p69
MWMM operand P register 69
R/W
0x00000000
Address : 0xff083514
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_p70
MWMM operand P register 70
R/W
0x00000000
Address : 0xff083518
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_p71
MWMM operand P register 71
R/W
0x00000000
Address : 0xff08351c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_p72
MWMM operand P register 72
R/W
0x00000000
Address : 0xff083520
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_p73
MWMM operand P register 73
R/W
0x00000000
Address : 0xff083524
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_p74
MWMM operand P register 74
R/W
0x00000000
Address : 0xff083528
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_p75
MWMM operand P register 75
R/W
0x00000000
Address : 0xff08352c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_p76
MWMM operand P register 76
R/W
0x00000000
Address : 0xff083530
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_p77
MWMM operand P register 77
R/W
0x00000000
Address : 0xff083534
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_p78
MWMM operand P register 78
R/W
0x00000000
Address : 0xff083538
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_p79
MWMM operand P register 79
R/W
0x00000000
Address : 0xff08353c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_p80
MWMM operand P register 80
R/W
0x00000000
Address : 0xff083540
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_p81
MWMM operand P register 81
R/W
0x00000000
Address : 0xff083544
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_p82
MWMM operand P register 82
R/W
0x00000000
Address : 0xff083548
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_p83
MWMM operand P register 83
R/W
0x00000000
Address : 0xff08354c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_p84
MWMM operand P register 84
R/W
0x00000000
Address : 0xff083550
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_p85
MWMM operand P register 85
R/W
0x00000000
Address : 0xff083554
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_p86
MWMM operand P register 86
R/W
0x00000000
Address : 0xff083558
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_p87
MWMM operand P register 87
R/W
0x00000000
Address : 0xff08355c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_p88
MWMM operand P register 88
R/W
0x00000000
Address : 0xff083560
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_p89
MWMM operand P register 89
R/W
0x00000000
Address : 0xff083564
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_p90
MWMM operand P register 90
R/W
0x00000000
Address : 0xff083568
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_p91
MWMM operand P register 91
R/W
0x00000000
Address : 0xff08356c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_p92
MWMM operand P register 92
R/W
0x00000000
Address : 0xff083570
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_p93
MWMM operand P register 93
R/W
0x00000000
Address : 0xff083574
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_p94
MWMM operand P register 94
R/W
0x00000000
Address : 0xff083578
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_p95
MWMM operand P register 95
R/W
0x00000000
Address : 0xff08357c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_p96
MWMM operand P register 96
R/W
0x00000000
Address : 0xff083580
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_p97
MWMM operand P register 97
R/W
0x00000000
Address : 0xff083584
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_p98
MWMM operand P register 98
R/W
0x00000000
Address : 0xff083588
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_p99
MWMM operand P register 99
R/W
0x00000000
Address : 0xff08358c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_p100
MWMM operand P register 100
R/W
0x00000000
Address : 0xff083590
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_p101
MWMM operand P register 101
R/W
0x00000000
Address : 0xff083594
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_p102
MWMM operand P register 102
R/W
0x00000000
Address : 0xff083598
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_p103
MWMM operand P register 103
R/W
0x00000000
Address : 0xff08359c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_p104
MWMM operand P register 104
R/W
0x00000000
Address : 0xff0835a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_p105
MWMM operand P register 105
R/W
0x00000000
Address : 0xff0835a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_p106
MWMM operand P register 106
R/W
0x00000000
Address : 0xff0835a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_p107
MWMM operand P register 107
R/W
0x00000000
Address : 0xff0835ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_p108
MWMM operand P register 108
R/W
0x00000000
Address : 0xff0835b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_p109
MWMM operand P register 109
R/W
0x00000000
Address : 0xff0835b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_p110
MWMM operand P register 110
R/W
0x00000000
Address : 0xff0835b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_p111
MWMM operand P register 111
R/W
0x00000000
Address : 0xff0835bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_p112
MWMM operand P register 112
R/W
0x00000000
Address : 0xff0835c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_p113
MWMM operand P register 113
R/W
0x00000000
Address : 0xff0835c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_p114
MWMM operand P register 114
R/W
0x00000000
Address : 0xff0835c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_p115
MWMM operand P register 115
R/W
0x00000000
Address : 0xff0835cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_p116
MWMM operand P register 116
R/W
0x00000000
Address : 0xff0835d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_p117
MWMM operand P register 117
R/W
0x00000000
Address : 0xff0835d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_p118
MWMM operand P register 118
R/W
0x00000000
Address : 0xff0835d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_p119
MWMM operand P register 119
R/W
0x00000000
Address : 0xff0835dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_p120
MWMM operand P register 120
R/W
0x00000000
Address : 0xff0835e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_p121
MWMM operand P register 121
R/W
0x00000000
Address : 0xff0835e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_p122
MWMM operand P register 122
R/W
0x00000000
Address : 0xff0835e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_p123
MWMM operand P register 123
R/W
0x00000000
Address : 0xff0835ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_p124
MWMM operand P register 124
R/W
0x00000000
Address : 0xff0835f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_p125
MWMM operand P register 125
R/W
0x00000000
Address : 0xff0835f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_p126
MWMM operand P register 126
R/W
0x00000000
Address : 0xff0835f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_p127
MWMM operand P register 127
R/W
0x00000000
Address : 0xff0835fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064


mtgy_op_b0
MWMM operand B register 0
R/W
0x00000000
Address : 0xff083600
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_b1
MWMM operand B register 1
R/W
0x00000000
Address : 0xff083604
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_b2
MWMM operand B register 2
R/W
0x00000000
Address : 0xff083608
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_b3
MWMM operand B register 3
R/W
0x00000000
Address : 0xff08360c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_b4
MWMM operand B register 4
R/W
0x00000000
Address : 0xff083610
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_b5
MWMM operand B register 5
R/W
0x00000000
Address : 0xff083614
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_b6
MWMM operand B register 6
R/W
0x00000000
Address : 0xff083618
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_b7
MWMM operand B register 7
R/W
0x00000000
Address : 0xff08361c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_b8
MWMM operand B register 8
R/W
0x00000000
Address : 0xff083620
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_b9
MWMM operand B register 9
R/W
0x00000000
Address : 0xff083624
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_b10
MWMM operand B register 10
R/W
0x00000000
Address : 0xff083628
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_b11
MWMM operand B register 11
R/W
0x00000000
Address : 0xff08362c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_b12
MWMM operand B register 12
R/W
0x00000000
Address : 0xff083630
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_b13
MWMM operand B register 13
R/W
0x00000000
Address : 0xff083634
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_b14
MWMM operand B register 14
R/W
0x00000000
Address : 0xff083638
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_b15
MWMM operand B register 15
R/W
0x00000000
Address : 0xff08363c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_b16
MWMM operand B register 16
R/W
0x00000000
Address : 0xff083640
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_b17
MWMM operand B register 17
R/W
0x00000000
Address : 0xff083644
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_b18
MWMM operand B register 18
R/W
0x00000000
Address : 0xff083648
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_b19
MWMM operand B register 19
R/W
0x00000000
Address : 0xff08364c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_b20
MWMM operand B register 20
R/W
0x00000000
Address : 0xff083650
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_b21
MWMM operand B register 21
R/W
0x00000000
Address : 0xff083654
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_b22
MWMM operand B register 22
R/W
0x00000000
Address : 0xff083658
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_b23
MWMM operand B register 23
R/W
0x00000000
Address : 0xff08365c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_b24
MWMM operand B register 24
R/W
0x00000000
Address : 0xff083660
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_b25
MWMM operand B register 25
R/W
0x00000000
Address : 0xff083664
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_b26
MWMM operand B register 26
R/W
0x00000000
Address : 0xff083668
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_b27
MWMM operand B register 27
R/W
0x00000000
Address : 0xff08366c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_b28
MWMM operand B register 28
R/W
0x00000000
Address : 0xff083670
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_b29
MWMM operand B register 29
R/W
0x00000000
Address : 0xff083674
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_b30
MWMM operand B register 30
R/W
0x00000000
Address : 0xff083678
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_b31
MWMM operand B register 31
R/W
0x00000000
Address : 0xff08367c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_b32
MWMM operand B register 32
R/W
0x00000000
Address : 0xff083680
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_b33
MWMM operand B register 33
R/W
0x00000000
Address : 0xff083684
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_b34
MWMM operand B register 34
R/W
0x00000000
Address : 0xff083688
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_b35
MWMM operand B register 35
R/W
0x00000000
Address : 0xff08368c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_b36
MWMM operand B register 36
R/W
0x00000000
Address : 0xff083690
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_b37
MWMM operand B register 37
R/W
0x00000000
Address : 0xff083694
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_b38
MWMM operand B register 38
R/W
0x00000000
Address : 0xff083698
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_b39
MWMM operand B register 39
R/W
0x00000000
Address : 0xff08369c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_b40
MWMM operand B register 40
R/W
0x00000000
Address : 0xff0836a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_b41
MWMM operand B register 41
R/W
0x00000000
Address : 0xff0836a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_b42
MWMM operand B register 42
R/W
0x00000000
Address : 0xff0836a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_b43
MWMM operand B register 43
R/W
0x00000000
Address : 0xff0836ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_b44
MWMM operand B register 44
R/W
0x00000000
Address : 0xff0836b0
Bits Reset value Name Description
31 - 0 0x0
val