Each of the four ADCs of the netX 90 is controlled by an individual MADC module. Each MADC module has its own register read/write bus (cpu_*), irq line (cpu_irq) and AHBL master port to write its measurements to the system memory. Therefore, the software can operate all ADCs completely independently from each other.
The common MADCC module generates the adc_clk_phase signal which schedules the generation of the adc_clk signals among the MADC modules, e.g. to prevent simultaneous occurrence of a rising edge on multiple adc_clks. The MADCC module also provides the static configuration signals to the analogue ADC blocks.
The sampling of the ADCs can be synchronized to the motor PWM (MPWM) module, either to the phase of the PWM signal (ECNT) or to the start of the dead time (DTEVT) between low and high side.
Figure1: netX90 MADC controller operating environment
Figure 2: ADC Timing Diagram (non scheduled adc_clk generation)
To minimize analogue interference between the ADCs it is advantageous to distribute the active (rising) edges of the four ADC’s adc_clks over time so that a minimum distance (e.g. one system clock cycle) is kept between the rising edges of the adc_clks.
To facilitate this the common MADCC module provides a cyclic counter signal adc_clk_phase counting continuously from 0 to MADCC_CFG.adc_clk_phase_max. Each MADC module can be assigned an adc_clk_phase. It will then delay the generation of the rising adc_clk edge until adc_clk_phase matches its assigned value. By this the active edges of all adc_clks can be distributed over the adc_clk phase given by the MADCC module (round robin scheduling). In a synchronized measurement the adc clock edge initiated by the trigger which ends the sampling phase is never delayed. It is recommended to set the adc clock period used by the MADC modules to be an integer multiple (e.g. 1x) of the adc_clk_phase period of the MADCC module and the sampling extension an integer multiple of the adc_clk, as only then the generated adc_clk periods have a constant length.